(CellTypeName "MCmdDrive")
(CreationTime "December 2, 1984 5:27:39 pm PST")
(CreatingUser "Spreitzer.pa")
(CreationSite "MilkyWay Sol III USA Xerox PARC ComputerResearch Aquaba")
(DerivingProgram "Rosemary Structure Capturer" "1954ef3230f9")
(Ports
	("PhA" (G D) (BIDIR))
	("PhB" (G D) (BIDIR))
	("nPhB" (G D) (BIDIR))
	("NoGrant" (G D) (BIDIR))
	("MCmd0" (G D) (BIDIR))
	("MCmd1" (G D) (BIDIR))
	("MCmd2" (G D) (BIDIR))
	("MCmd3" (G D) (BIDIR))
	("Vdd" (G D) (BIDIR))
	("Gnd" (G D) (BIDIR))
	("BiasMinus" (G D) (BIDIR))
	("BiasPlus" (G D) (BIDIR)))

(PrivateFollows)
(N "BiasMinus" (G D))
(N "BiasPlus" (G D))
(N "Gnd" (G D))
(N "MCmd0" (G D))
(N "MCmd1" (G D))
(N "MCmd2" (G D))
(N "MCmd3" (G D))
(N "NoGrant" (G D))
(N "PhA" (G D))
(N "PhB" (G D))
(N "Vdd" (G D))
(N "nPhB" (G D))
(N "t1" (G D))
(N "t2" (G D))
(N "t3" (G D))
(N "t4" (G D))
(N "t5" (G D))
(N "t6" (G D))
(N "t7" (G D))
(N "t8" (G D))
(N "t9" (G D))
(PN "PhA" "PhA")
(PN "PhB" "PhB")
(PN "nPhB" "nPhB")
(PN "NoGrant" "NoGrant")
(PN "MCmd0" "MCmd0")
(PN "MCmd1" "MCmd1")
(PN "MCmd2" "MCmd2")
(PN "MCmd3" "MCmd3")
(PN "Vdd" "Vdd")
(PN "Gnd" "Gnd")
(PN "BiasMinus" "BiasMinus")
(PN "BiasPlus" "BiasPlus")
(CI "g1" "NAND" (G D)
	(CIC
		("in1" "t1")
		("in2" "PhB")
		("out" "t2")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "g2" "NAND" (G D)
	(CIC
		("in1" "t2")
		("in2" "t3")
		("out" "t4")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "g3" "OAI" (G D)
	(CIC
		("ino1" "PhA")
		("ino2" "t5")
		("ina1" "t4")
		("out" "t3")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "g4" "NAND" (G D)
	(CIC
		("in1" "t2")
		("in2" "t6")
		("out" "t5")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "g5" "NAND" (G D)
	(CIC
		("in1" "t5")
		("in2" "t7")
		("out" "t6")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "i1" "Inverter" (G D)
	(CIC
		("in" "NoGrant")
		("out" "t9")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "i2" "Inverter" (G D)
	(CIC
		("in" "PhA")
		("out" "t7")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "i3" "Inverter" (G D)
	(CIC
		("in" "t4")
		("out" "t8")
		("Vdd" "Vdd")
		("Gnd" "Gnd")))
(CI "l1" "InvertingLatch" (G D)
	(CIC
		("Clock" "PhA")
		("D" "t9")
		("nQ" "t1")
		("Vdd" "Vdd")
		("Gnd" "Gnd")
		("BiasMinus" "BiasMinus")))
(CI "m0" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D)
	(CIC
		("gate" "t8")
		("ch1" "Vdd")
		("ch2" "MCmd0")))
(CI "m1" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D)
	(CIC
		("gate" "t8")
		("ch1" "Vdd")
		("ch2" "MCmd1")))
(CI "m2" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D)
	(CIC
		("gate" "t8")
		("ch1" "Vdd")
		("ch2" "MCmd2")))
(CI "m3" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D)
	(CIC
		("gate" "t8")
		("ch1" "Vdd")
		("ch2" "MCmd3")))
(CI "s1" "StaticPrecharge" (G D)
	(CIC
		("clock" "nPhB")
		("out" "NoGrant")
		("Vdd" "Vdd")
		("Gnd" "Gnd")
		("BiasPlus" "BiasPlus")))