DIRECTORY AMTypes, Asserting, Basics, Core, CoreRecord, IO, PrincOps, Rope, RedBlackTree, RoseBehavior, RoseBindPrivate, RoseControl, RoseEvents, RosePrivates, RoseWireTypes, VFonts; RoseSimTypes: CEDAR DEFINITIONS = BEGIN OPEN RoseWireTypes; CellType: TYPE = Core.CellType; CellInstance: TYPE = CoreRecord.CellInstance; CellInstanceList: TYPE = CoreRecord.CellInstanceList; Error: ERROR [msg: ROPE, data: REF ANY _ NIL]; Warning: SIGNAL [msg: ROPE, data: REF ANY _ NIL]; Stop: SIGNAL [msg: ROPE, data: REF ANY _ NIL]; roseWireTypeKey: ATOM; roseWireKey: ATOM; roseCellKey: ATOM; RoseWireList: TYPE = LIST OF RoseWire; RoseWire: TYPE = REF RoseWireRep; RoseWireRep: TYPE = RECORD [ schIn: Scheduling, core: Wire, type: RoseWireType, subwires: RoseWireS, valPtr: Ptr _ nilPtr, bitCount: INT _ 0, capStrength: Strength _ charge, holdStrength: Strength _ charge, winnerStrength: Strength _ charge, switchConnections: SlotList _ NIL, byStrength: ARRAY Strength OF StrengthRingHead _ ALL[emptyHead], found, XPhobic, isInput: BOOLEAN _ FALSE, nextPerturbed, nextAffected, nextDelayed, prevDelayed: RoseWire _ NIL--compiler can't handle: notInWireList--, watchers: ARRAY Priority OF WatcherList _ ALL[NIL], other: Assertions _ NIL]; WireGroup: TYPE = {aboveLeaf, leaf, belowLeaf}; notInWireList: RoseWire; SlotList: TYPE = LIST OF Slot; Slot: TYPE = RECORD [ cell: RoseCellInstance, effectivePortIndex: EffectivePortIndex ]; nilSlot: Slot = [NIL, nilEffectivePortIndex]; ModelSlot: TYPE = RECORD [ cell: RoseCellInstance, portPath: PortPath]; nilModelSlot: ModelSlot = [NIL, NIL]; StrengthRingHead: TYPE = RECORD [first, last: Slot]; emptyHead: StrengthRingHead = [head, head]; head: Slot --don't look:-- = nilSlot; Priority: TYPE = {ordinary, high}; roseCellInstanceKey: ATOM; RoseCellType: TYPE = REF RoseCellTypeRep; RoseCellTypeRep: TYPE = RECORD [ core: CellType, behaviorClass: RoseBindPrivate.BehaviorClass, wireTypes: ARRAY WireFlavor OF RoseWireType, other: Assertions _ NIL]; RoseCellInstance: TYPE = REF RoseCellInstanceRep; RoseCellInstanceRep: TYPE = RECORD [ schIn: Scheduling, core: CellInstance, args: REF ANY, type: RoseCellType, effectivePorts: EffectivePortS, connectedWires: RoseWireS, schedNext, nextNeeded, nextNoted: RoseCellInstance _ NIL--notInCellList--, newIO, oldIO, switchIO, newDrive, oldDrive: REF ANY, locked: BOOLEAN _ FALSE, hasTransducedPort: BOOL _ FALSE, affectedFlags: AffectedFlags _ ALL[FALSE], initQed, propQed, initUDed, propUDed: BOOLEAN _ FALSE, state: REF ANY, schedWatchers, evalWatchers: WatcherList _ NIL, other: Assertions _ NIL]; notInCellList: RoseCellInstance; AffectedFlags: TYPE = ARRAY Speciality OF BOOLEAN; Speciality: TYPE = {transducedToSwitch, modeledAsSwitch}; RoseWireS: TYPE = REF RoseWireSeq; RoseWireSeq: TYPE = RECORD [wires: SEQUENCE length: EffectivePortIndex OF RoseWire]; EffectivePortS: TYPE = REF EffectivePortSeq; EffectivePortSeq: TYPE = RECORD [ports: SEQUENCE length: EffectivePortIndex OF EffectivePort]; EffectivePort: TYPE = RECORD [ switch, newSimple, oldSimple, newDrive, oldDrive: Ptr, type: RoseWireType, implType: RoseWireType, path: PortPath _ NIL, strengthNext, strengthPrev: Slot _ nilSlot, curStrength: Drive _ test, input, output, XPhobic, transduced: BOOLEAN, other: Assertions _ NIL ]; EffectivePortIndex: TYPE = CARDINAL; nilEffectivePortIndex: EffectivePortIndex = LAST[EffectivePortIndex]; Simulation: TYPE = REF SimulationRec; SimulationRec: TYPE = RECORD [ flatRootType: CellType, rootRecordType: CoreRecord.RecordCellType, sch: Scheduling, cth: CellTestHandle _ NIL, other: Assertions _ NIL]; Scheduling: TYPE = REF SchedulingRep; SchedulingRep: TYPE = RECORD [ sim: Simulation, schedFirst, schedLast, firstNeeded: RoseCellInstance _ NIL, firstPerturbed, firstAffected, firstDelayed, lastDelayed: RoseWire _ NIL, running: BOOL _ FALSE ]; CellTestHandle: TYPE = REF CellTestHandleRep; CellTestHandleRep: TYPE = RECORD [ sim: Simulation, testerCT, testeeCT: CellType, testerCI, testeeCI: CellInstance, switchInstructions: REF ANY _ NIL, simpleInstructions: REF ANY _ NIL, driveInstructions: REF ANY _ NIL, driveInstructionsAsPtr: Ptr _ nilPtr, testerRCT, testeeRCT: RoseCellType, testerRCI, testeeRCI: RoseCellInstance _ NIL, instructionFields: EffectivePortS _ NIL, test: CellTest _ NIL, ctl: TestControl _ NIL ]; TestControl: TYPE = REF TestControlRec; TestControlRec: TYPE = RECORD [stopBefore, stopAfter: BOOL _ FALSE]; CellTest: TYPE = REF CellTestRec; CellTestRec: TYPE = RECORD [ testProc: RoseControl.TestProc, testData: REF ANY _ NIL, stateToo: BOOL _ FALSE ]; END. €RoseSimTypes.Mesa Spreitzer, September 30, 1985 7:06:27 pm PDT Barth, August 16, 1985 4:55:42 pm PDT This module defines the data types used by the Rosemary simulator. For to get the RoseWireType from a Core.Wire. Only doable for a Core.Wire in WireGroup leaf. For to get the RoseWire, if any, from a Core.Wire. The RoseWires make a disjoint cover of the Core Wires. For to get the RoseCellInstance from a Core CellInstance. Size of value. A roseWire has an intrinsic strength (its capacitance). The capacitance used by the simulator; =capStrength, unless being externally pegged at input. For simple wires, the strength of the strongest drivers. The RoseWireType is responsible for computing "isInput". "ordinary" is for ordinary mortals, like breakpoints "high" is for things like the display, which should be updated first For to get the RoseCellInstance from a Core Cell Instance. There will only be one for leaves of the simulation. The type the CellType's eval procs deal in. IF transduced THEN type transduced to ELSE type. The selector of this relative to the entire public wire. Links around the strength ring, and which ring currently in. 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