SwitchInv.mesa
Copyright © 1985 by Xerox Corporation. All rights reversed.
Barth, August 1, 1985 2:31:39 pm PDT
Spreitzer, October 2, 1985 3:15:13 pm PDT
DIRECTORY BasicTime, BitTwiddling, Core, CoreOps, CoreProperties, CoreRecord, CoreTransistor, GetMe, IO, Rope, RoseBehavior, RoseBind;
SwitchInv:
CEDAR
PROGRAM
IMPORTS CoreOps, CoreProperties, CoreRecord, CoreTransistor, RoseBind
=
BEGIN OPEN Core, CoreOps, CoreProperties, CoreRecord, RoseBind;
DefineInverter:
PROC [design: Design]
RETURNS [ct: CellType] = {
in: Wire = CreateAtomWire["in"];
out: Wire = CreateAtomWire["out"];
vdd: Wire = CreateAtomWire["vdd"];
gnd: Wire = CreateAtomWire["gnd"];
pw: Wire = CreateRecordWire["inverterPublic", LIST[in, out, vdd, gnd]];
nE: CellType = CoreTransistor.Create[[nE]];
pE: CellType = CoreTransistor.Create[[pE]];
rct: RecordCellType ←
NEW [RecordCellTypeRec ← [
internalWire: CreateRecordWire["inverterInternal", LIST[in, out, vdd, gnd]],
instances:
LIST[
NEW [CellInstanceRec ← [
name: "pu",
actualWire: CreateRecordWire[NIL, LIST[in, out, vdd, vdd]],
type: pE
]],
NEW [CellInstanceRec ← [
name: "pd",
actualWire: CreateRecordWire[NIL, LIST[in, out, gnd, gnd]],
type: nE
]]
]
]];
pw.properties ← PutProp[pw.properties, RoseBind.switchWire, $T];
pw.properties ← PutProp[pw.properties, RoseBind.testerSwitchWire, $T];
ct ←
NEW [CellTypeRec ← [
name: "SwitchInv",
publicWire: pw,
class: recordCellClass,
data: rct
]];
InsertCellType[design, nE];
InsertCellType[design, pE];
InsertCellType[design, ct];
};
END.