<> <> DIRECTORY AMTypes, Asserting, Basics, Core, CoreRecordCells, IO, Rope, RedBlackTree, RoseEvents; RoseTypes: CEDAR DEFINITIONS = <> BEGIN Error: ERROR [msg: ROPE, data: REF ANY _ NIL]; Warning: SIGNAL [msg: ROPE, data: REF ANY _ NIL]; Stop: SIGNAL [msg: ROPE, data: REF ANY _ NIL]; LORA: TYPE = LIST OF REF ANY; ROPE: TYPE = Rope.ROPE; LOR: TYPE = LIST OF ROPE; STREAM: TYPE = IO.STREAM; TV: TYPE = AMTypes.TV; Assertion: TYPE = Asserting.Assertion; Assertions: TYPE = Asserting.Assertions; SymbolTable: TYPE = RedBlackTree.Table; WatcherList: TYPE = RoseEvents.WatcherList; Watcher: TYPE = RoseEvents.Watcher; Wire: TYPE = Core.Wire; CellType: TYPE = Core.CellType; CellInstance: TYPE = CoreRecordCells.Instance; WordPtr: TYPE = LONG POINTER TO CARDINAL; Ptr: TYPE = PrincOps.BitAddress; nilPtr: Ptr = [word: NIL, bit: 0]; Field: TYPE = RECORD [ wordOffset: CARDINAL, bitOffset: BitOffset, bitCount: CARDINAL]; BitOffset: TYPE = [0 .. Basics.bitsPerWord); noField: Field = [LAST[CARDINAL], LAST[BitOffset], LAST[CARDINAL]]; wireType: ATOM; --to get the RoseWireType from a Core.Wire RoseWireType: TYPE = REF RoseWireTypeRec; RoseWireTypeRec: TYPE = RECORD [ class: RoseWireTypeClass, typeData: REF ANY, other: Assertions _ NIL]; RoseWireTypeClass: TYPE = REF RoseWireTypeClassRec; RoseWireTypeClassRec: TYPE = RECORD [ <> UserDescription: PROC [RoseWireType] RETURNS [ROPE], ListFormats: PROC [RoseWireType] RETURNS [LOR], GetFormat: PROC [RoseWireType, ROPE] RETURNS [Format], MesaForSelf: PROC [RoseWireType] RETURNS [Mesa], <> <> SelectorOffset: PROC [RoseWireType, Selector] RETURNS [NAT] _ NIL, <> SubType: PROC [RoseWireType, Selector] RETURNS [RoseWireType] _ NIL, <> Bits: PROC [RoseWireType] RETURNS [container, data, leftPad: INT], <> MesaRepresentation: PROC [RoseWireType] RETURNS [Mesa], <> MesaRepAux: PROC [RoseWireType] RETURNS [Mesa] _ NIL, <> <> simple: BOOL _ TRUE, Equivalent: PROC [self, other: RoseWireType] RETURNS [BOOL] _ NIL, <> SwitchEquivalent: PROC [RoseWireType] RETURNS [RoseWireType] _ NIL, <> SimpleEquivalent: PROC [RoseWireType] RETURNS [RoseWireType] _ NIL, <> Transduce: PROC [fromS: Strength, fromT, toT: RoseWireType, fromP, toP: Ptr] _ NIL, InitWire: PROC [wire: Wire, steady: BOOL] _ NIL, <> InitPort: PROC [Wire, Ptr] _ NIL, InitQ, InitUD: PROC [Wire] _ NIL, NewVal: PROC [Wire] RETURNS [delay: BOOL] _ NIL, CopyVal: PROC [nt: RoseWireType, from, to: Ptr] _ NIL, NewQ, NewUD: PROC [Wire, Ptr] RETURNS [BOOL] _ NIL, QFromWire, UDFromWire, ValFromWire, SetWire: PROC [Wire, Ptr] _ NIL, CompareUD: PROC [nt: RoseWireType, p1, p2: Ptr] RETURNS [BOOL] _ NIL ]; Mesa: TYPE = RECORD [mesa: ROPE, directory, imports: LOR _ NIL]; Selector: TYPE = RECORD [variant: SELECT kind: * FROM whole => [], number, field => [index: INT], range, fields => [first, count: INT, up: BOOL], ENDCASE]; Strength: TYPE = DriveLevel[ignore .. input]; DriveLevel: TYPE = { test,--for TestProcs to say "test it for me" see,--for TestProcs to say "I'll test it" ignore,--from a TestProc it means neither driven nor tested; in simulation it means no strength at all chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, chargeVeryStrong, driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, driveVeryStrong, input--the strongest drive level: how circuit inputs are driven }; Drive: TYPE = REF DriveRep; <> DriveRep: TYPE = RECORD [ tag: DriveTagType, <> drives: PACKED SEQUENCE COMPUTED NAT--portIndex-- OF DriveLevel]; DriveTagType: TYPE = CARDINAL; Format: TYPE = REF FormatRep; FormatRep: TYPE = RECORD [ FormatValue: PROC [RoseWireType, Format, Ptr] RETURNS [ROPE], ParseValue: PROC [RoseWireType, Format, Ptr, STREAM] RETURNS [BOOLEAN], FormatTest: PROC [RoseWireType, Format, WireTest] RETURNS [ROPE], ParseTest: PROC [RoseWireType, Format, STREAM] RETURNS [BOOLEAN, WireTest], MaxWidth: PROC [RoseWireType, Format, VFonts.Font] RETURNS [INT], formatData: REF ANY _ NIL, key: ROPE ]; WireTest: TYPE = RECORD [proc: WireTestProc, data: REF ANY]; WireTestProc: TYPE = PROC [ where: Ptr, testData: REF ANY, roseWireType: RoseWireType] RETURNS [passes: BOOLEAN]; RoseWire: TYPE = REF RoseWireRep; RoseWireRep: TYPE = RECORD [ core: Wire, type: RoseWireType, valRef: REF ANY _ NIL, valPtr: Ptr _ nilPtr, <> <> <> ctnPtr: Ptr _ nilPtr, <> bitCount: INT _ 0, <> strength: Strength _ charge, <> currentStrength: Strength _ charge, <> cap: REAL _ 0, <> cellIn: Cell _ NIL, <> <> strIn: Structure, switchConnections: SlotList _ NIL, byStrength: ARRAY Strength OF StrengthRingHead _ ALL[emptyHead], found, XPhobic, isInput: BOOLEAN _ FALSE, <> nextPerturbed, nextAffected, nextDelayed, prevDelayed: RoseWire _ NIL--compiler can't handle: notInWireList--, watchers: ARRAY Priority OF WatcherList _ ALL[NIL], significances: WireSignificances, designNext: RoseWire _ NIL--compiler can't handle: notInWireList--, <> implNext: RoseWire _ NIL--compiler can't handle: notInWireList--, <> parentPieces: PieceList _ NIL, <> <> childPieces: PieceList _ NIL, <> <> other: Assertions _ NIL]; NodeSignificances: TYPE = ARRAY NodeSignificance OF BOOL; NodeSignificance: TYPE = {fromDesign, inImpl}; designOnly: NodeSignificances = [TRUE, FALSE]; implOnly: NodeSignificances = [FALSE, TRUE]; <> <> <> <> <> <> notInWireList: RoseWire; SlotList: TYPE = LIST OF Slot; Slot: TYPE = RECORD [ cell: Cell, effectivePortIndex: EffectivePortIndex ]; nilSlot: Slot = [NIL, nilEffectivePortIndex]; StrengthRingHead: TYPE = RECORD [first, last: Slot]; emptyHead: StrengthRingHead = [head, head]; head: Slot --don't look:-- = nilSlot; StrengthRingElement: TYPE = REF StrengthRingElementRep; StrengthRingElementRep: TYPE = RECORD [ next, prev: StrengthRingElement, slot: Slot]; PieceList: TYPE = LIST OF Piece; Piece: TYPE = RECORD [ twardDesign, twardImpl: Wire, reln: Selector <> ]; RoseCellInstance: TYPE = REF RoseCellInstanceRep; RoseCellInstanceRep: TYPE = RECORD [ core: CellInstance, nextInstance: RoseCellInstance, sim: Simulation, parent, leftChild, rightSibling: RoseCellInstance, firstInternalNode: Node, internalNodes, components: SymbolTable, interfaceNodes: NodeS, other: Assertions, substantiality: CellSubstantiality, expansion: ExpandDecision, realCellStuff: RealCellStuff -- non-NIL only for Real Cells ]; notInCellList: RoseCellInstance; RealCellStuff: TYPE = REF RealCellStuffRep; RealCellStuffRep: TYPE = RECORD [ effectivePorts: EffectivePorts, implNodes: NodeS, schedNext, nextNeeded, nextNoted: RoseCellInstance _ NIL--notInCellList--, newIO, oldIO, switchIO, newDriveAsAny, oldDriveAsAny: REF ANY, newIOAsWP, oldIOAsWP, switchIOAsWP: WordPtr, newDrive, oldDrive: Drive, locked: BOOLEAN _ FALSE, hasTransducedPort: BOOL _ FALSE, affectedFlags: AffectedFlags _ ALL[FALSE], initQed, propQed, initUDed, propUDed: BOOLEAN _ FALSE, state: REF ANY, evals: EvalProcs, schedWatchers, evalWatchers: WatcherList _ NIL]; AffectedFlags: TYPE = ARRAY Speciality OF BOOLEAN; Speciality: TYPE = {transducedToSwitch, modeledAsSwitch}; END.