[Indigo]<Rosemary>4.0>RoseTypes.Mesa!1

RoseTypes.Mesa

Spreitzer, July 26, 1985 4:26:30 pm PDT

DIRECTORY AMTypes, Asserting, Basics, Core, CoreRecordCells, IO, Rope, RedBlackTree, RoseEvents;

RoseTypes: CEDAR DEFINITIONS =

This module defines the data types used in Rosemary circuit representations, as well as the data types used by the Rosemary simulator.

BEGIN

Error: ERROR [msg: ROPE, data: REF ANY ← NIL];

Warning: SIGNAL [msg: ROPE, data: REF ANY ← NIL];

Stop: SIGNAL [msg: ROPE, data: REF ANY ← NIL];

LORA: TYPE = LIST OF REF ANY;

ROPE: TYPE = Rope.ROPE;

LOR: TYPE = LIST OF ROPE;

STREAM: TYPE = IO.STREAM;

TV: TYPE = AMTypes.TV;

Assertion: TYPE = Asserting.Assertion;

Assertions: TYPE = Asserting.Assertions;

SymbolTable: TYPE = RedBlackTree.Table;

WatcherList: TYPE = RoseEvents.WatcherList;

Watcher: TYPE = RoseEvents.Watcher;

Wire: TYPE = Core.Wire;

CellType: TYPE = Core.CellType;

CellInstance: TYPE = CoreRecordCells.Instance;

WordPtr: TYPE = LONG POINTER TO CARDINAL;

Ptr: TYPE = PrincOps.BitAddress;

nilPtr: Ptr = [word: NIL, bit: 0];

Field: TYPE = RECORD [

wordOffset: CARDINAL,

bitOffset: BitOffset,

bitCount: CARDINAL];

BitOffset: TYPE = [0 .. Basics.bitsPerWord);

noField: Field = [LAST[CARDINAL], LAST[BitOffset], LAST[CARDINAL]];

wireType: ATOM; --to get the RoseWireType from a Core.Wire

RoseWireType: TYPE = REF RoseWireTypeRec;

RoseWireTypeRec: TYPE = RECORD [

class: RoseWireTypeClass,

typeData: REF ANY,

other: Assertions ← NIL];

RoseWireTypeClass: TYPE = REF RoseWireTypeClassRec;

RoseWireTypeClassRec: TYPE = RECORD [

Interface

UserDescription: PROC [RoseWireType] RETURNS [ROPE],

ListFormats: PROC [RoseWireType] RETURNS [LOR],

GetFormat: PROC [RoseWireType, ROPE] RETURNS [Format],

MesaForSelf: PROC [RoseWireType] RETURNS [Mesa],

a Mesa expression that evaluates to this RoseWireType

Structure

SelectorOffset: PROC [RoseWireType, Selector] RETURNS [NAT] ← NIL,

Offset, in bits, from begin of interesting data (not container) to begin of selected data.

SubType: PROC [RoseWireType, Selector] RETURNS [RoseWireType] ← NIL,

Representation

Bits: PROC [RoseWireType] RETURNS [container, data, leftPad: INT],

The number of bits occupied by the MesaRepresentation is returned in `container'; the number of interesting bits is returned in `data'; the number of bits in the container in front of the interesting bits is returned in `leftPad'.

MesaRepresentation: PROC [RoseWireType] RETURNS [Mesa],

the Mesa type of the representation

MesaRepAux: PROC [RoseWireType] RETURNS [Mesa] ← NIL,

Mesa code (e.g. declaration) to establish mesa type

Behavior

simple: BOOL ← TRUE,

Equivalent: PROC [self, other: RoseWireType] RETURNS [BOOL] ← NIL,

Says whether we can freely copy bits between them.

SwitchEquivalent: PROC [RoseWireType] RETURNS [RoseWireType] ← NIL,

Gives the type to transduce to, when necessary.

SimpleEquivalent: PROC [RoseWireType] RETURNS [RoseWireType] ← NIL,

For a switch-level type, gives a simple type that can transduce to it.

Transduce: PROC [fromS: Strength, fromT, toT: RoseWireType, fromP, toP: Ptr] ← NIL,

InitWire: PROC [wire: Wire, steady: BOOL] ← NIL,

If steady, initialize for steady-state work; otherwise, for initialization work.

InitPort: PROC [Wire, Ptr] ← NIL,

InitQ, InitUD: PROC [Wire] ← NIL,

NewVal: PROC [Wire] RETURNS [delay: BOOL] ← NIL,

CopyVal: PROC [nt: RoseWireType, from, to: Ptr] ← NIL,

NewQ, NewUD: PROC [Wire, Ptr] RETURNS [BOOL] ← NIL,

QFromWire, UDFromWire, ValFromWire, SetWire: PROC [Wire, Ptr] ← NIL,

CompareUD: PROC [nt: RoseWireType, p1, p2: Ptr] RETURNS [BOOL] ← NIL

];

Mesa: TYPE = RECORD [mesa: ROPE, directory, imports: LOR ← NIL];

Selector: TYPE = RECORD [variant: SELECT kind: * FROM

whole => [],

number, field => [index: INT],

range, fields => [first, count: INT, up: BOOL],

ENDCASE];

Strength: TYPE = DriveLevel[ignore .. input];

DriveLevel: TYPE = {

test,--for TestProcs to say "test it for me"

see,--for TestProcs to say "I'll test it"

ignore,--from a TestProc it means neither driven nor tested; in simulation it means no strength at all

chargeWeak, chargeMediumWeak,

charge,

chargeMediumStrong, chargeStrong, chargeVeryStrong,

driveWeak, driveMediumWeak,

drive,

driveMediumStrong, driveStrong, driveVeryStrong,

input--the strongest drive level: how circuit inputs are driven

};

Drive: TYPE = REF DriveRep;

The layout of a drive record should correspond to this.

DriveRep: TYPE = RECORD [

tag: DriveTagType,

tag is not meaningful; it only provides space for CellTypes that need it.

drives: PACKED SEQUENCE COMPUTED NAT--portIndex-- OF DriveLevel];

DriveTagType: TYPE = CARDINAL;

Format: TYPE = REF FormatRep;

FormatRep: TYPE = RECORD [

FormatValue: PROC [RoseWireType, Format, Ptr] RETURNS [ROPE],

ParseValue: PROC [RoseWireType, Format, Ptr, STREAM] RETURNS [BOOLEAN],

FormatTest: PROC [RoseWireType, Format, WireTest] RETURNS [ROPE],

ParseTest: PROC [RoseWireType, Format, STREAM] RETURNS [BOOLEAN, WireTest],

MaxWidth: PROC [RoseWireType, Format, VFonts.Font] RETURNS [INT],

formatData: REF ANY ← NIL,

key: ROPE

];

WireTest: TYPE = RECORD [proc: WireTestProc, data: REF ANY];

WireTestProc: TYPE = PROC

[

where: Ptr,

testData: REF ANY,

roseWireType: RoseWireType]

RETURNS [passes: BOOLEAN];

RoseWire: TYPE = REF RoseWireRep;

RoseWireRep: TYPE = RECORD [

core: Wire,

type: RoseWireType,

valRef: REF ANY ← NIL,

valPtr: Ptr ← nilPtr,

Pointer to the interesting data.

A fromDesign roseWire keeps a copy of its entire value;

An implOnly roseWire keeps here a pointer into one of its parents.

ctnPtr: Ptr ← nilPtr,

Pointer to the container of the data, for a fromDesign roseWire.

bitCount: INT ← 0,

Size of value.

strength: Strength ← charge,

A roseWire has an intrinsic strength (its capacitance).

currentStrength: Strength ← charge,

For simple wires, the strength of the strongest drivers.

cap: REAL ← 0,

Some jokers may want to accumulate strength here.

cellIn: Cell ← NIL,

A fromDesign roseWire tells who created it;

an implOnly roseWire notes lowest common ancestor of contributing fromDesign wires.

strIn: Structure,

switchConnections: SlotList ← NIL,

byStrength: ARRAY Strength OF StrengthRingHead ← ALL[emptyHead],

found, XPhobic, isInput: BOOLEAN ← FALSE,

The RoseWireType is responsible for maintaining "isInput".

nextPerturbed, nextAffected, nextDelayed, prevDelayed: RoseWire ← NIL--compiler can't handle: notInWireList--,

watchers: ARRAY Priority OF WatcherList ← ALL[NIL],

significances: WireSignificances,

designNext: RoseWire ← NIL--compiler can't handle: notInWireList--,

For a fromDesign roseWire, link in order of def.

implNext: RoseWire ← NIL--compiler can't handle: notInWireList--,

For an inImpl roseWire, link to others in strIn.

parentPieces: PieceList ← NIL,

For a implOnly roseWire, the containing designOnly wires, and pointers into their values;

for a NOT fromDesign roseWire during creation, the breaking toward design wires.

childPieces: PieceList ← NIL,

For a designOnly roseWire, the breaking into implOnly wires;

for a NOT inImpl roseWire during creation, the breaking toward impl wires.

other: Assertions ← NIL];

NodeSignificances: TYPE = ARRAY NodeSignificance OF BOOL;

NodeSignificance: TYPE = {fromDesign, inImpl};

designOnly: NodeSignificances = [TRUE, FALSE];

implOnly: NodeSignificances = [FALSE, TRUE];

A fromDesign node appears in the designer's model; it comes from an ExpandProc.

An inImpl node is used by the simulator for communicating values.

An implOnly node is used by some client code to implement something (e.g, split/joiners); it corresponds to a piece of a fromDesign node (or nodes).

A designOnly node is used to relate the designer's model to what the simulator is doing.

A [TRUE, TRUE] node is that happy coincidence between the designer's model and what the simulator is doing.

A [FALSE, FALSE] node was an implOnly node that got further decomposed.

notInWireList: RoseWire;

SlotList: TYPE = LIST OF Slot;

Slot: TYPE = RECORD [

cell: Cell,

effectivePortIndex: EffectivePortIndex

];

nilSlot: Slot = [NIL, nilEffectivePortIndex];

StrengthRingHead: TYPE = RECORD [first, last: Slot];

emptyHead: StrengthRingHead = [head, head];

head: Slot --don't look:-- = nilSlot;

StrengthRingElement: TYPE = REF StrengthRingElementRep;

StrengthRingElementRep: TYPE = RECORD [

next, prev: StrengthRingElement,

slot: Slot];

PieceList: TYPE = LIST OF Piece;

Piece: TYPE = RECORD [

twardDesign, twardImpl: Wire,

reln: Selector

twardDesign.reln=twardImpl

];

RoseCellInstance: TYPE = REF RoseCellInstanceRep;

RoseCellInstanceRep: TYPE = RECORD [

core: CellInstance,

nextInstance: RoseCellInstance,

sim: Simulation,

parent, leftChild, rightSibling: RoseCellInstance,

firstInternalNode: Node,

internalNodes, components: SymbolTable,

interfaceNodes: NodeS,

other: Assertions,

substantiality: CellSubstantiality,

expansion: ExpandDecision,

realCellStuff: RealCellStuff -- non-NIL only for Real Cells

];

notInCellList: RoseCellInstance;

RealCellStuff: TYPE = REF RealCellStuffRep;

RealCellStuffRep: TYPE = RECORD [

effectivePorts: EffectivePorts,

implNodes: NodeS,

schedNext, nextNeeded, nextNoted: RoseCellInstance ← NIL--notInCellList--,

newIO, oldIO, switchIO, newDriveAsAny, oldDriveAsAny: REF ANY,

newIOAsWP, oldIOAsWP, switchIOAsWP: WordPtr,

newDrive, oldDrive: Drive,

locked: BOOLEAN ← FALSE,

hasTransducedPort: BOOL ← FALSE,

affectedFlags: AffectedFlags ← ALL[FALSE],

initQed, propQed, initUDed, propUDed: BOOLEAN ← FALSE,

state: REF ANY,

evals: EvalProcs,

schedWatchers, evalWatchers: WatcherList ← NIL];

AffectedFlags: TYPE = ARRAY Speciality OF BOOLEAN;

Speciality: TYPE = {transducedToSwitch, modeledAsSwitch};

END.