[Indigo]<Rosemary>4.0>RoseSimTypes.Mesa!22

RoseSimTypes.Mesa

Spreitzer, September 30, 1985 7:06:27 pm PDT

Barth, August 16, 1985 4:55:42 pm PDT

DIRECTORY AMTypes, Asserting, Basics, Core, CoreRecord, IO, PrincOps, Rope, RedBlackTree, RoseBehavior, RoseBindPrivate, RoseControl, RoseEvents, RosePrivates, RoseWireTypes, VFonts;

RoseSimTypes: CEDAR DEFINITIONS =

This module defines the data types used by the Rosemary simulator.

BEGIN OPEN RoseWireTypes;

CellType: TYPE = Core.CellType;

CellInstance: TYPE = CoreRecord.CellInstance;

CellInstanceList: TYPE = CoreRecord.CellInstanceList;

Error: ERROR [msg: ROPE, data: REF ANY ← NIL];

Warning: SIGNAL [msg: ROPE, data: REF ANY ← NIL];

Stop: SIGNAL [msg: ROPE, data: REF ANY ← NIL];

roseWireTypeKey: ATOM;

For to get the RoseWireType from a Core.Wire.

Only doable for a Core.Wire in WireGroup leaf.

roseWireKey: ATOM;

For to get the RoseWire, if any, from a Core.Wire.

The RoseWires make a disjoint cover of the Core Wires.

roseCellKey: ATOM;

For to get the RoseCellInstance from a Core CellInstance.

RoseWireList: TYPE = LIST OF RoseWire;

RoseWire: TYPE = REF RoseWireRep;

RoseWireRep: TYPE = RECORD [

schIn: Scheduling,

core: Wire,

type: RoseWireType,

subwires: RoseWireS,

valPtr: Ptr ← nilPtr,

bitCount: INT ← 0,

Size of value.

capStrength: Strength ← charge,

A roseWire has an intrinsic strength (its capacitance).

holdStrength: Strength ← charge,

The capacitance used by the simulator; =capStrength, unless being externally pegged at input.

winnerStrength: Strength ← charge,

For simple wires, the strength of the strongest drivers.

switchConnections: SlotList ← NIL,

byStrength: ARRAY Strength OF StrengthRingHead ← ALL[emptyHead],

found, XPhobic, isInput: BOOLEAN ← FALSE,

The RoseWireType is responsible for computing "isInput".

nextPerturbed, nextAffected, nextDelayed, prevDelayed: RoseWire ← NIL--compiler can't handle: notInWireList--,

watchers: ARRAY Priority OF WatcherList ← ALL[NIL],

other: Assertions ← NIL];

WireGroup: TYPE = {aboveLeaf, leaf, belowLeaf};

notInWireList: RoseWire;

SlotList: TYPE = LIST OF Slot;

Slot: TYPE = RECORD [

cell: RoseCellInstance,

effectivePortIndex: EffectivePortIndex

];

nilSlot: Slot = [NIL, nilEffectivePortIndex];

ModelSlot: TYPE = RECORD [

cell: RoseCellInstance,

portPath: PortPath];

nilModelSlot: ModelSlot = [NIL, NIL];

StrengthRingHead: TYPE = RECORD [first, last: Slot];

emptyHead: StrengthRingHead = [head, head];

head: Slot --don't look:-- = nilSlot;

Priority: TYPE = {ordinary, high};

"ordinary" is for ordinary mortals, like breakpoints

"high" is for things like the display, which should be updated first

roseCellInstanceKey: ATOM;

For to get the RoseCellInstance from a Core Cell Instance.

There will only be one for leaves of the simulation.

RoseCellType: TYPE = REF RoseCellTypeRep;

RoseCellTypeRep: TYPE = RECORD [

core: CellType,

behaviorClass: RoseBindPrivate.BehaviorClass,

wireTypes: ARRAY WireFlavor OF RoseWireType,

other: Assertions ← NIL];

RoseCellInstance: TYPE = REF RoseCellInstanceRep;

RoseCellInstanceRep: TYPE = RECORD [

schIn: Scheduling,

core: CellInstance,

args: REF ANY,

type: RoseCellType,

effectivePorts: EffectivePortS,

connectedWires: RoseWireS,

schedNext, nextNeeded, nextNoted: RoseCellInstance ← NIL--notInCellList--,

newIO, oldIO, switchIO, newDrive, oldDrive: REF ANY,

locked: BOOLEAN ← FALSE,

hasTransducedPort: BOOL ← FALSE,

affectedFlags: AffectedFlags ← ALL[FALSE],

initQed, propQed, initUDed, propUDed: BOOLEAN ← FALSE,

state: REF ANY,

schedWatchers, evalWatchers: WatcherList ← NIL,

other: Assertions ← NIL];

notInCellList: RoseCellInstance;

AffectedFlags: TYPE = ARRAY Speciality OF BOOLEAN;

Speciality: TYPE = {transducedToSwitch, modeledAsSwitch};

RoseWireS: TYPE = REF RoseWireSeq;

RoseWireSeq: TYPE = RECORD [wires: SEQUENCE length: EffectivePortIndex OF RoseWire];

EffectivePortS: TYPE = REF EffectivePortSeq;

EffectivePortSeq: TYPE = RECORD [ports: SEQUENCE length: EffectivePortIndex OF EffectivePort];

EffectivePort: TYPE = RECORD [

switch, newSimple, oldSimple, newDrive, oldDrive: Ptr,

type: RoseWireType,

The type the CellType's eval procs deal in.

implType: RoseWireType,

IF transduced THEN type transduced to ELSE type.

path: PortPath ← NIL,

The selector of this relative to the entire public wire.

strengthNext, strengthPrev: Slot ← nilSlot, curStrength: Drive ← test,

Links around the strength ring, and which ring currently in.

input, output, XPhobic, transduced: BOOLEAN,

other: Assertions ← NIL

];

EffectivePortIndex: TYPE = CARDINAL;

nilEffectivePortIndex: EffectivePortIndex = LAST[EffectivePortIndex];

Simulation: TYPE = REF SimulationRec;

SimulationRec: TYPE = RECORD [

flatRootType: CellType,

rootRecordType: CoreRecord.RecordCellType,

sch: Scheduling,

cth: CellTestHandle ← NIL,

other: Assertions ← NIL];

Scheduling: TYPE = REF SchedulingRep;

SchedulingRep: TYPE = RECORD [

sim: Simulation,

schedFirst, schedLast, firstNeeded: RoseCellInstance ← NIL,

firstPerturbed, firstAffected, firstDelayed, lastDelayed: RoseWire ← NIL,

running: BOOL ← FALSE

];

CellTestHandle: TYPE = REF CellTestHandleRep;

CellTestHandleRep: TYPE = RECORD [

sim: Simulation,

testerCT, testeeCT: CellType,

testerCI, testeeCI: CellInstance,

switchInstructions: REF ANY ← NIL,

simpleInstructions: REF ANY ← NIL,

driveInstructions: REF ANY ← NIL,

driveInstructionsAsPtr: Ptr ← nilPtr,

testerRCT, testeeRCT: RoseCellType,

testerRCI, testeeRCI: RoseCellInstance ← NIL,

instructionFields: EffectivePortS ← NIL,

Same types, different pointers.

test: CellTest ← NIL,

ctl: TestControl ← NIL

];

TestControl: TYPE = REF TestControlRec;

TestControlRec: TYPE = RECORD [stopBefore, stopAfter: BOOL ← FALSE];

CellTest: TYPE = REF CellTestRec;

CellTestRec: TYPE = RECORD [

testProc: RoseControl.TestProc,

testData: REF ANY ← NIL,

stateToo: BOOL ← FALSE

];

END.