Directory Basics; Imports Asserting, BiasTypes, Rope, RoseCreate, RoseTypes, SwitchTypes; Open SwitchTypes, RoseCreate, RoseTypes; InterfaceCedar Mode: TYPE = {Enhancement, Depletion}; ; CEDAR bpw: NAT = Basics.bitsPerWord; Conductance: TYPE = {Off, On, Indeterminate}; ComputeState: ARRAY Mode OF ARRAY BOOL--positive-- OF ARRAY Level OF Conductance = [ Enhancement: [[On, Off, Indeterminate], [Off, On, Indeterminate]], Depletion: [ALL[On], ALL[On]]]; TransSimpleIORef: TYPE = REF TransSimpleIORec; TransSimpleIORec: TYPE = RECORD [bgate: BiasTypes.BiasHolder]; TransSwitchIORef: TYPE = REF TransSwitchIORec; TransSwitchIORec: TYPE = RECORD [sgate, ch1, ch2: SwitchVal]; TransDriveRec: TYPE = RECORD [tag: DriveTagType, drive: PACKED ARRAY TransistorPort OF DriveLevel]; TransistorPort: TYPE = {gate, ch1, ch2, fill}; BiasToLevel: ARRAY BiasTypes.Bias OF Level = [H, L]; classes: ARRAY --positive--BOOL OF ARRAY Mode OF ROPE _ [ FALSE: [Enhancement: "pE", Depletion: "pD"], TRUE: [Enhancement: "nE", Depletion: "nD"]]; checkUni: BOOL _ TRUE; Bitch: PROC [cell: Cell] = { SIGNAL Warning[Rope.Cat["Backward flow across unidirectional transistor ", LongCellName[cell], "!"]]; }; ; Transistor: LAMBDA [ strength: |RoseTypes.Strength _ drive|, positive: |BOOL _ TRUE|, mode: |Mode _ Enhancement|, unidirectional: |BOOL _ FALSE|, biased: |BOOL _ FALSE|, offStrength: |RoseTypes.Strength _ SwitchTypes.none|] RETURN CELLTYPE AutoName PortsProc ports _ NEW [PortsRep[3]]; ports[0] _ [ simple: [0, bpw-1, 1], switch: [0, 0, bpw], name: "gate", type: IF biased THEN BiasTypes.biasType ELSE bitType, input: TRUE]; ports[1] _ [ simple: noField, switch: [1, 0, bpw], name: "ch1", type: bitType, input: TRUE, output: NOT unidirectional]; ports[2] _ [ simple: noField, switch: [2, 0, bpw], name: "ch2", type: bitType, input: NOT unidirectional, output: TRUE]; IF NOT unidirectional THEN { ports[1].other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[1].other]; ports[2].other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[2].other]; }; InitCTProps other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], classes[positive][mode]], inAdditionTo: other]; SimpleIOAux RecType TransSimpleIORec SwitchIOAux RecType TransSwitchIORec DriveAux RecType TransDriveRec State conductance: Conductance Initializer conductance _ ComputeState[mode][positive][SELECT biased FROM FALSE => sw.sgate.val, TRUE => BiasToLevel[bgate.bias], ENDCASE => ERROR]; EvalSimple IF mode = Enhancement AND biased THEN { new: Conductance _ ComputeState[mode][positive][SELECT biased FROM FALSE => sw.sgate.val, TRUE => BiasToLevel[bgate.bias], ENDCASE => ERROR]; IF new # conductance THEN { conductance _ new; IF NOT unidirectional THEN perturb[1]; perturb[2]; } }; ValsChanged IF mode = Enhancement AND NOT biased THEN { new: Conductance _ ComputeState[mode][positive][SELECT biased FROM FALSE => sgate.val, TRUE => BiasToLevel[newIO.bgate.bias], ENDCASE => ERROR]; IF new # conductance THEN { conductance _ new; IF NOT unidirectional THEN perturb[1]; perturb[2]; } }; EnumerateVicinity NotOff: PROC RETURNS [no: BOOL] = INLINE { no _ SELECT conductance FROM On, Indeterminate => TRUE, Off => offStrength > none, ENDCASE => ERROR}; SELECT portIndex FROM 0 => NULL; 1, 2 => IF NotOff[] THEN consume[3-portIndex]; ENDCASE => ERROR; PropQ cs: Strength = SELECT conductance FROM On => strength, Off, Indeterminate => offStrength, ENDCASE => ERROR; IF cs > none THEN { IF unidirectional THEN NULL ELSE ch1.s[q] _ MAX[ch1.s[q], MIN[cs, ch2.s[q]]]; ch2.s[q] _ MAX[ch2.s[q], MIN[cs, ch1.s[q]]]; }; InitUD cs: Strength = SELECT conductance FROM On => strength, Off, Indeterminate => offStrength, ENDCASE => ERROR; IF unidirectional AND checkUni AND ch1.s[q] < MIN[cs, ch2.s[q]] THEN Bitch[cell]; PropUD cs: Strength = SELECT conductance FROM On, Indeterminate => strength, Off => offStrength, ENDCASE => ERROR; IF cs > none THEN { IF unidirectional THEN NULL ELSE { ch1.s[u] _ MAX[ch1.s[u], MIN[cs, ch2.s[u]]]; ch1.s[d] _ MAX[ch1.s[d], MIN[cs, ch2.s[d]]]; }; ch2.s[u] _ MAX[ch2.s[u], MIN[cs, ch1.s[u]]]; ch2.s[d] _ MAX[ch2.s[d], MIN[cs, ch1.s[d]]]; }; FinalUD cs: Strength = SELECT conductance FROM On, Indeterminate => strength, Off => offStrength, ENDCASE => ERROR; IF cs > none AND unidirectional AND checkUni THEN { IF ch1.s[u] < Block[MIN[cs, ch2.s[u]], ch1.s[q]] THEN Bitch[cell]; IF ch1.s[d] < Block[MIN[cs, ch2.s[d]], ch1.s[q]] THEN Bitch[cell]; }; ENDCELLTYPE; nE: Transistor[]; nD: Transistor[mode: Depletion, strength: driveWeak]; pE: Transistor[positive: FALSE]; unE: Transistor[unidirectional: TRUE]; unD: Transistor[mode: Depletion, strength: driveWeak, unidirectional: TRUE]; upE: Transistor[positive: FALSE, unidirectional: TRUE]; wpu: Transistor[strength: driveWeak, positive: FALSE, unidirectional: TRUE]; wpd: Transistor[offStrength: driveWeak, unidirectional: TRUE, biased: TRUE] êTransistors.Rose Last Edited by: Spreitzer, July 15, 1985 10:19:50 pm PDT Last Edited by: Gasbarro, August 17, 1984 11:22:10 am PDT conductance _ SELECT mode FROM Enhancement => Indeterminate, Depletion => On, ENDCASE => ERROR; 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