DIRECTORY RoseCreate, RoseTypes, SwitchTypes, Transistors; RoseTest: CEDAR PROGRAM IMPORTS RoseCreate, SwitchTypes, Transistors = BEGIN OPEN SwitchTypes, RoseCreate, RoseTypes; nE: ROPE _ Transistors.Transistor[[]].name; nD: ROPE _ Transistors.Transistor[[driveWeak, TRUE, Depletion]].name; ExpandTest1: PROC [thisCell: Cell, to: ExpansionReceiver] --ExpandProc-- = BEGIN vdd: Node _ to.class.NodeInstance[to.instance, "vdd", bitType, "H", NIL, refInput]; gnd: Node _ to.class.NodeInstance[to.instance, "gnd", bitType, "L", NIL, refInput]; in: Node _ to.class.NodeInstance[to.instance, "in", bitType]; out: Node _ to.class.NodeInstance[to.instance, "out", bitType]; pd: Cell _ to.class.CellInstance[to.instance, "pd", nE, "in, gnd, out"]; pu: Cell _ to.class.CellInstance[to.instance, "pu", nD, "out, vdd, out"]; END; InterterIORef: TYPE = REF InverterIORec; InverterIORec: TYPE = MACHINE DEPENDENT RECORD [ vdd(0:16-bitsPerSwitchVal..15): SwitchVal, gnd(1:16-bitsPerSwitchVal..15): SwitchVal, in(2:16-bitsPerSwitchVal..15): SwitchVal, out(3:16-bitsPerSwitchVal..15): SwitchVal]; inverterPorts: Ports _ NEW [PortsRep[4]]; CreateInverterIO: PROC [ct: CellType] RETURNS [ioAsAny: REF ANY]--IOCreator-- = BEGIN ioAsAny _ NEW [InverterIORec]; END; pass: ROPE _ Transistors.Transistor[[drive, TRUE, Enhancement, TRUE]].name; pullup: ROPE _ Transistors.Transistor[[driveWeak, TRUE, Depletion, TRUE]].name; ExpandInverter: PROC [thisCell: Cell, to: ExpansionReceiver]--ExpandProc-- = BEGIN pd: Cell _ to.class.CellInstance[to.instance, "pd", pass, "in, gnd, out"]; pu: Cell _ to.class.CellInstance[to.instance, "pu", pullup, "out, vdd, out"]; END; ExpandTest2: PROC [thisCell: Cell, to: ExpansionReceiver]--ExpandProc-- = BEGIN vdd: Node _ to.class.NodeInstance[to.instance, "vdd", bitType, "H", NIL, refInput]; gnd: Node _ to.class.NodeInstance[to.instance, "gnd", bitType, "L", NIL, refInput]; in1: Node _ to.class.NodeInstance[to.instance, "in1", bitType, NIL, NIL, refInput]; in2: Node _ to.class.NodeInstance[to.instance, "in2", bitType, NIL, NIL, refInput]; out1: Node _ to.class.NodeInstance[to.instance, "out1", bitType]; out2: Node _ to.class.NodeInstance[to.instance, "out2", bitType]; sel1: Node _ to.class.NodeInstance[to.instance, "sel1", bitType, NIL, NIL, refInput]; sel2: Node _ to.class.NodeInstance[to.instance, "sel2", bitType, NIL, NIL, refInput]; ans: Node _ to.class.NodeInstance[to.instance, "ans", bitType]; inv1: Cell _ to.class.CellInstance[to.instance, "inv1", "Inverter", "in: in1, out: out1"]; inv2: Cell _ to.class.CellInstance[to.instance, "inv2", "Inverter", "in: in2, out: out2"]; pass1: Cell _ to.class.CellInstance[to.instance, "pass1", nE, "sel1, out1, ans"]; pass2: Cell _ to.class.CellInstance[to.instance, "pass2", nE, "sel2, out2, ans"]; END; Setup: PROC = BEGIN [] _ RegisterCellType[ name: "Test1", expandProc: ExpandTest1, evals: [], ports: NEW [PortsRep[0]] ]; inverterPorts[0] _ [0, 1, "vdd", bitType, TRUE, FALSE]; inverterPorts[1] _ [1, 1, "gnd", bitType, TRUE, FALSE]; inverterPorts[2] _ [2, 1, "in", bitType, TRUE, FALSE]; inverterPorts[3] _ [3, 1, "out", bitType, TRUE, TRUE]; [] _ RegisterCellType[ name: "Inverter", ioCreator: CreateInverterIO, expandProc: ExpandInverter, evals: [], ports: inverterPorts ]; [] _ RegisterCellType[ name: "Test2", expandProc: ExpandTest2, evals: [], ports: NEW [PortsRep[0]] ]; END; Setup[]; END. lRoseTest.Mesa Last Edited by: Spreitzer, January 23, 1985 11:16:13 pm PST fill0(0:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), fill3(3:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), Κ– "cedar" style˜J™ J™;J˜IcodešΟk œ1˜:K˜šΠbxœœ˜Kšœ'˜.—K˜Kšœœ$˜.K˜Kšœœ#˜+Kšœœ&œ˜EK˜šΟn œœ)Οcœ˜JKš˜KšœDœ ˜SKšœDœ ˜SK˜=K˜?KšœH˜HKšœI˜IKšœ˜—K˜Kšœœœ˜(š œœœ œœ˜0K™FK˜*K™FK˜*K™FK˜)K™FK˜+—K˜Kšœœ˜)K˜š Ÿœœœ œœ  œ˜OKš˜Kšœ œ˜Kšœ˜—K˜Kšœœ"œœ˜KKšœœ&œ œ˜OK˜šŸœœ( œ˜LKš˜KšœJ˜JKšœM˜MKšœ˜—K˜šŸ œœ( œ˜IKš˜KšœDœ ˜SKšœDœ ˜SKšœ?œœ ˜SKšœ?œœ ˜SK˜AK˜AKšœAœœ ˜UKšœAœœ ˜UK˜?K˜ZK˜ZK˜QK˜QKšœ˜—K˜šŸœœ˜ Kš˜˜K˜K˜K˜ Kšœœ˜K˜—K˜Kšœ*œœ˜7Kšœ*œœ˜7Kšœ)œœ˜6Kšœ*œœ˜6˜K˜K˜K˜K˜ Kšœ˜K˜—K˜˜K˜K˜K˜ Kšœœ˜K˜—Kšœ˜—K˜K˜K˜Kšœ˜—…— @Β