<> <> <> <> <> DIRECTORY RoseTypes, Transistors, RoseCreate, Basics, Asserting, BiasTypes, Rope, SwitchTypes, PrintTV, AMBridge, IO; TransistorsImpl: CEDAR PROGRAM IMPORTS RoseCreate, Asserting, BiasTypes, Rope, RoseTypes, SwitchTypes, PrintTV, AMBridge, IO EXPORTS Transistors = BEGIN OPEN RoseTypes, Transistors, SwitchTypes, RoseCreate; <> RegisterCells: PROC = BEGIN END; otherss: SymbolTable _ RoseCreate.GetOtherss["Transistors.partsAssertions"]; <> bpw: NAT = Basics.bitsPerWord; Conductance: TYPE = {Off, On, Indeterminate}; ComputeState: ARRAY Mode OF ARRAY BOOL--positive-- OF ARRAY Level OF Conductance = [ Enhancement: [[On, Off, Indeterminate], [Off, On, Indeterminate]], Depletion: [ALL[On], ALL[On]]]; TransSimpleIORef: TYPE = REF TransSimpleIORec; TransSimpleIORec: TYPE = RECORD [bgate: BiasTypes.BiasHolder]; TransSwitchIORef: TYPE = REF TransSwitchIORec; TransSwitchIORec: TYPE = RECORD [sgate, ch1, ch2: SwitchVal]; TransDriveRec: TYPE = RECORD [tag: DriveTagType, drive: PACKED ARRAY TransistorPort OF DriveLevel]; TransistorPort: TYPE = {gate, ch1, ch2, fill}; BiasToLevel: ARRAY BiasTypes.Bias OF Level = [H, L]; classes: ARRAY --positive--BOOL OF ARRAY Mode OF ROPE _ [ FALSE: [Enhancement: "pE", Depletion: "pD"], TRUE: [Enhancement: "nE", Depletion: "nD"]]; checkUni: BOOL _ TRUE; Bitch: PROC [cell: Cell] = { SIGNAL Warning[Rope.Cat["Backward flow across unidirectional transistor ", LongCellName[cell], "!"]]; }; OldTransistor: TYPE = RECORD [args: TransistorArgs, ct: CellType]; oldTransistor: LIST OF OldTransistor _ NIL; Transistor: PUBLIC PROC [args: TransistorArgs] RETURNS [ct: CellType] = BEGIN FOR old: LIST OF OldTransistor _ oldTransistor, old.rest WHILE old # NIL DO IF old.first.args = args THEN RETURN [old.first.ct] ENDLOOP; ct _ RoseCreate.RegisterCellType[name: TransistorName[args], expandProc: NIL, ioCreator: CreateTransistorIO, driveCreator: CreateTransistorDrive, initializer: InitializeTransistor, evals: [ValsChanged: TransistorValsChanged, PropQ: TransistorPropQ, InitUD: TransistorInitUD, PropUD: TransistorPropUD, FinalUD: TransistorFinalUD, EvalSimple: TransistorEvalSimple, EnumerateVicinity: TransistorEnumerateVicinity], tests: LIST[], ports: CreateTransistorPorts[args] , typeData: NEW [TransistorArgs _ args], other: InitialTransistorProps[args]]; oldTransistor _ CONS[[args, ct], oldTransistor]; END; TransistorName: PROC [args: TransistorArgs] RETURNS [name: ROPE] = { to: IO.STREAM _ IO.ROS[]; to.PutRope["Transistor"]; TRUSTED {PrintTV.Print[tv: AMBridge.TVForReferent[NEW [TransistorArgs _ args]], put: to, depth: 2]}; name _ IO.RopeFromROS[to]}; CreateTransistorIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = { args: REF TransistorArgs _ NARROW[ct.typeData]; {OPEN args; ioAsAny _ IF switch THEN NEW[TransSwitchIORec] ELSE NEW[TransSimpleIORec]; }; }; CreateTransistorDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = { args: REF TransistorArgs _ NARROW[ct.typeData]; {OPEN args; driveAsAny _ NEW[TransDriveRec]; }; }; CreateTransistorPorts: PROC [args: TransistorArgs] RETURNS [ports: Ports] = BEGIN OPEN args; ports _ NEW [PortsRep[3]]; ports[0] _ [ simple: [0, bpw-1, 1], switch: [0, 0, bpw], name: "gate", type: IF biased THEN BiasTypes.biasType ELSE bitType, input: TRUE]; ports[1] _ [ simple: noField, switch: [1, 0, bpw], name: "ch1", type: bitType, input: TRUE, output: NOT unidirectional]; ports[2] _ [ simple: noField, switch: [2, 0, bpw], name: "ch2", type: bitType, input: NOT unidirectional, output: TRUE]; IF NOT unidirectional THEN { ports[1].other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[1].other]; ports[2].other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[2].other]; }; END; TransistorStateRef: TYPE = REF TransistorStateRec; TransistorStateRec: TYPE = RECORD [ conductance: Conductance ]; InitializeTransistor: Initializer = { args: REF TransistorArgs _ NARROW [cell.type.typeData]; {OPEN args; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NEW[TransistorStateRec]; cell.realCellStuff.state _ state; BEGIN OPEN drive, newIO, state; < Indeterminate, Depletion => On, ENDCASE => ERROR;>> conductance _ ComputeState[mode][positive][SELECT biased FROM FALSE => sw.sgate.val, TRUE => BiasToLevel[bgate.bias], ENDCASE => ERROR]; END; }; }; TransistorValsChanged: SimpleEval = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN sw, drive, args, state; IF mode = Enhancement AND NOT biased THEN { new: Conductance _ ComputeState[mode][positive][SELECT biased FROM FALSE => sgate.val, TRUE => BiasToLevel[newIO.bgate.bias], ENDCASE => ERROR]; IF new # conductance THEN { conductance _ new; IF NOT unidirectional THEN perturb[1]; perturb[2]; } }; END; END; TransistorPropQ: CellProc = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN sw, args, state; cs: Strength = SELECT conductance FROM On => strength, Off, Indeterminate => offStrength, ENDCASE => ERROR; IF cs > none THEN { IF unidirectional THEN NULL ELSE ch1.s[q] _ MAX[ch1.s[q], MIN[cs, ch2.s[q]]]; ch2.s[q] _ MAX[ch2.s[q], MIN[cs, ch1.s[q]]]; }; END; END; TransistorInitUD: CellProc = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN sw, args, state; cs: Strength = SELECT conductance FROM On => strength, Off, Indeterminate => offStrength, ENDCASE => ERROR; IF unidirectional AND checkUni AND ch1.s[q] < MIN[cs, ch2.s[q]] THEN Bitch[cell]; END; END; TransistorPropUD: CellProc = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN sw, args, state; cs: Strength = SELECT conductance FROM On, Indeterminate => strength, Off => offStrength, ENDCASE => ERROR; IF cs > none THEN { IF unidirectional THEN NULL ELSE { ch1.s[u] _ MAX[ch1.s[u], MIN[cs, ch2.s[u]]]; ch1.s[d] _ MAX[ch1.s[d], MIN[cs, ch2.s[d]]]; }; ch2.s[u] _ MAX[ch2.s[u], MIN[cs, ch1.s[u]]]; ch2.s[d] _ MAX[ch2.s[d], MIN[cs, ch1.s[d]]]; }; END; END; TransistorFinalUD: CellProc = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN sw, args, state; cs: Strength = SELECT conductance FROM On, Indeterminate => strength, Off => offStrength, ENDCASE => ERROR; IF cs > none AND unidirectional AND checkUni THEN { IF ch1.s[u] < Block[MIN[cs, ch2.s[u]], ch1.s[q]] THEN Bitch[cell]; IF ch1.s[d] < Block[MIN[cs, ch2.s[d]], ch1.s[q]] THEN Bitch[cell]; }; END; END; TransistorEvalSimple: SimpleEval = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN drive, newIO, args, state; IF mode = Enhancement AND biased THEN { new: Conductance _ ComputeState[mode][positive][SELECT biased FROM FALSE => sw.sgate.val, TRUE => BiasToLevel[bgate.bias], ENDCASE => ERROR]; IF new # conductance THEN { conductance _ new; IF NOT unidirectional THEN perturb[1]; perturb[2]; } }; END; END; TransistorEnumerateVicinity: PROC [cell: Cell, portIndex: PortIndex, evenIfInput: BOOL _ FALSE, consume: PROC [PortIndex]] = BEGIN args: REF TransistorArgs _ NARROW[cell.type.typeData]; drive: REF TransDriveRec _ NARROW[cell.realCellStuff.newDriveAsAny]; sw: REF TransSwitchIORec _ NARROW[cell.realCellStuff.switchIO]; newIO: REF TransSimpleIORec _ NARROW[cell.realCellStuff.newIO]; state: TransistorStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN args, state; NotOff: PROC RETURNS [no: BOOL] = INLINE { no _ SELECT conductance FROM On, Indeterminate => TRUE, Off => offStrength > none, ENDCASE => ERROR}; SELECT portIndex FROM 0 => NULL; 1, 2 => IF NotOff[] THEN consume[3-portIndex]; ENDCASE => ERROR; END; END; InitialTransistorProps: PROC [args: TransistorArgs] RETURNS [other: Assertions] = { other _ NIL; --designer's part: --{OPEN args; other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], classes[positive][mode]], inAdditionTo: other]; }; }; nE: PUBLIC CellType _ Transistor[[]]; nD: PUBLIC CellType _ Transistor[[mode:Depletion, strength:driveWeak]]; pE: PUBLIC CellType _ Transistor[[positive:FALSE]]; unE: PUBLIC CellType _ Transistor[[unidirectional:TRUE]]; unD: PUBLIC CellType _ Transistor[[mode:Depletion, strength:driveWeak, unidirectional:TRUE]]; upE: PUBLIC CellType _ Transistor[[positive:FALSE, unidirectional:TRUE]]; wpu: PUBLIC CellType _ Transistor[[strength:driveWeak, positive:FALSE, unidirectional:TRUE]]; wpd: PUBLIC CellType _ Transistor[[offStrength:driveWeak, unidirectional:TRUE, biased:TRUE]]; RegisterCells[]; END.