TransistorsImpl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from Transistors.Rose of July 15, 1985 10:19:50 pm PDT
created for Spreitzer.pa
created at September 5, 1985 12:29:06 pm PDT
DIRECTORY
RoseTypes, Transistors, RoseCreate, Basics, Asserting, BiasTypes, Rope, SwitchTypes, PrintTV, AMBridge, IO;
TransistorsImpl: CEDAR PROGRAM
IMPORTS RoseCreate, Asserting, BiasTypes, Rope, RoseTypes, SwitchTypes, PrintTV, AMBridge, IO
EXPORTS Transistors
= BEGIN OPEN
RoseTypes, Transistors, SwitchTypes, RoseCreate;
Signal Type decls
RegisterCells: PROC =
BEGIN
END;
otherss: SymbolTable ← RoseCreate.GetOtherss["Transistors.partsAssertions"];
explicitly requested CEDAR:
bpw: NAT = Basics.bitsPerWord;
Conductance: TYPE = {Off, On, Indeterminate};
ComputeState: ARRAY Mode OF ARRAY BOOL--positive-- OF ARRAY Level OF Conductance = [
Enhancement: [[On, Off, Indeterminate], [Off, On, Indeterminate]],
Depletion: [ALL[On], ALL[On]]];
TransSimpleIORef: TYPE = REF TransSimpleIORec;
TransSimpleIORec: TYPE = RECORD [bgate: BiasTypes.BiasHolder];
TransSwitchIORef: TYPE = REF TransSwitchIORec;
TransSwitchIORec: TYPE = RECORD [sgate, ch1, ch2: SwitchVal];
TransDriveRec: TYPE = RECORD [tag: DriveTagType, drive: PACKED ARRAY TransistorPort OF DriveLevel];
TransistorPort: TYPE = {gate, ch1, ch2, fill};
BiasToLevel: ARRAY BiasTypes.Bias OF Level = [H, L];
classes: ARRAY --positive--BOOL OF ARRAY Mode OF ROPE ← [
FALSE: [Enhancement: "pE", Depletion: "pD"],
TRUE: [Enhancement: "nE", Depletion: "nD"]];
checkUni: BOOL ← TRUE;
Bitch: PROC [cell: Cell] = {
SIGNAL Warning[Rope.Cat["Backward flow across unidirectional transistor ", LongCellName[cell], "!"]];
};
OldTransistor: TYPE = RECORD [args: TransistorArgs, ct: CellType];
oldTransistor: LIST OF OldTransistor ← NIL;
Transistor: PUBLIC PROC [args: TransistorArgs] RETURNS [ct: CellType]
= BEGIN
FOR old: LIST OF OldTransistor ← oldTransistor, old.rest WHILE old # NIL DO
IF old.first.args = args THEN RETURN [old.first.ct]
ENDLOOP;
ct ← RoseCreate.RegisterCellType[name: TransistorName[args],
expandProc: NIL,
ioCreator: CreateTransistorIO, driveCreator: CreateTransistorDrive, initializer: InitializeTransistor,
evals: [ValsChanged: TransistorValsChanged, PropQ: TransistorPropQ, InitUD: TransistorInitUD, PropUD: TransistorPropUD, FinalUD: TransistorFinalUD, EvalSimple: TransistorEvalSimple, EnumerateVicinity: TransistorEnumerateVicinity],
tests: LIST[],
ports: CreateTransistorPorts[args]
,
typeData: NEW [TransistorArgs ← args],
other: InitialTransistorProps[args]];
oldTransistor ← CONS[[args, ct], oldTransistor];
END;
TransistorName: PROC [args: TransistorArgs] RETURNS [name: ROPE] = {
to: IO.STREAM ← IO.ROS[]; to.PutRope["Transistor"];
TRUSTED {PrintTV.Print[tv: AMBridge.TVForReferent[NEW [TransistorArgs ← args]], put: to, depth: 2]};
name ← IO.RopeFromROS[to]};
CreateTransistorIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
args: REF TransistorArgs ← NARROW[ct.typeData];
{OPEN args;
ioAsAny ← IF switch THEN NEW[TransSwitchIORec] ELSE NEW[TransSimpleIORec];
};
};
CreateTransistorDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
args: REF TransistorArgs ← NARROW[ct.typeData];
{OPEN args;
driveAsAny ← NEW[TransDriveRec];
};
};
CreateTransistorPorts: PROC [args: TransistorArgs] RETURNS [ports: Ports] =
BEGIN OPEN args;
ports ← NEW [PortsRep[3]];
ports[0] ← [
simple: [0, bpw-1, 1],
switch: [0, 0, bpw],
name: "gate",
type: IF biased THEN BiasTypes.biasType ELSE bitType,
input: TRUE];
ports[1] ← [
simple: noField,
switch: [1, 0, bpw],
name: "ch1",
type: bitType,
input: TRUE,
output: NOT unidirectional];
ports[2] ← [
simple: noField,
switch: [2, 0, bpw],
name: "ch2",
type: bitType,
input: NOT unidirectional,
output: TRUE];
IF NOT unidirectional THEN {
ports[1].other ← Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[1].other];
ports[2].other ← Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[2].other];
};
END;
TransistorStateRef: TYPE = REF TransistorStateRec;
TransistorStateRec: TYPE = RECORD [
conductance: Conductance
];
InitializeTransistor: Initializer = {
args: REF TransistorArgs ← NARROW [cell.type.typeData];
{OPEN args;
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NEW[TransistorStateRec];
cell.realCellStuff.state ← state;
BEGIN OPEN drive, newIO, state;
conductance ← SELECT mode FROM Enhancement => Indeterminate, Depletion => On, ENDCASE => ERROR;
conductance ← ComputeState[mode][positive][SELECT biased FROM FALSE => sw.sgate.val, TRUE => BiasToLevel[bgate.bias], ENDCASE => ERROR];
END;
};
};
TransistorValsChanged: SimpleEval =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, drive, args, state;
IF mode = Enhancement AND NOT biased THEN {
new: Conductance ← ComputeState[mode][positive][SELECT biased FROM FALSE => sgate.val, TRUE => BiasToLevel[newIO.bgate.bias], ENDCASE => ERROR];
IF new # conductance THEN {
conductance ← new;
IF NOT unidirectional THEN perturb[1];
perturb[2];
}
};
END;
END;
TransistorPropQ: CellProc =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On => strength,
Off, Indeterminate => offStrength,
ENDCASE => ERROR;
IF cs > none THEN {
IF unidirectional THEN NULL ELSE
ch1.s[q] ← MAX[ch1.s[q], MIN[cs, ch2.s[q]]];
ch2.s[q] ← MAX[ch2.s[q], MIN[cs, ch1.s[q]]];
};
END;
END;
TransistorInitUD: CellProc =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On => strength,
Off, Indeterminate => offStrength,
ENDCASE => ERROR;
IF unidirectional AND checkUni AND ch1.s[q] < MIN[cs, ch2.s[q]] THEN Bitch[cell];
END;
END;
TransistorPropUD: CellProc =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On, Indeterminate => strength,
Off => offStrength,
ENDCASE => ERROR;
IF cs > none THEN {
IF unidirectional THEN NULL
ELSE {
ch1.s[u] ← MAX[ch1.s[u], MIN[cs, ch2.s[u]]];
ch1.s[d] ← MAX[ch1.s[d], MIN[cs, ch2.s[d]]];
};
ch2.s[u] ← MAX[ch2.s[u], MIN[cs, ch1.s[u]]];
ch2.s[d] ← MAX[ch2.s[d], MIN[cs, ch1.s[d]]];
};
END;
END;
TransistorFinalUD: CellProc =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On, Indeterminate => strength,
Off => offStrength,
ENDCASE => ERROR;
IF cs > none AND unidirectional AND checkUni THEN {
IF ch1.s[u] < Block[MIN[cs, ch2.s[u]], ch1.s[q]] THEN Bitch[cell];
IF ch1.s[d] < Block[MIN[cs, ch2.s[d]], ch1.s[q]] THEN Bitch[cell];
};
END;
END;
TransistorEvalSimple: SimpleEval =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, args, state;
IF mode = Enhancement AND biased THEN {
new: Conductance ← ComputeState[mode][positive][SELECT biased FROM FALSE => sw.sgate.val, TRUE => BiasToLevel[bgate.bias], ENDCASE => ERROR];
IF new # conductance THEN {
conductance ← new;
IF NOT unidirectional THEN perturb[1];
perturb[2];
}
};
END;
END;
TransistorEnumerateVicinity: PROC [cell: Cell, portIndex: PortIndex, evenIfInput: BOOL ← FALSE, consume: PROC [PortIndex]] =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
drive: REF TransDriveRec ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: REF TransSwitchIORec ← NARROW[cell.realCellStuff.switchIO];
newIO: REF TransSimpleIORec ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN args, state;
NotOff: PROC RETURNS [no: BOOL] = INLINE {
no ← SELECT conductance FROM
On, Indeterminate => TRUE,
Off => offStrength > none,
ENDCASE => ERROR};
SELECT portIndex FROM
0 => NULL;
1, 2 => IF NotOff[] THEN consume[3-portIndex];
ENDCASE => ERROR;
END;
END;
InitialTransistorProps: PROC [args: TransistorArgs] RETURNS [other: Assertions] = {
other ← NIL;
--designer's part: --{OPEN args;
other ← Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], classes[positive][mode]], inAdditionTo: other];
};
};
nE: PUBLIC CellType ← Transistor[[]];
nD: PUBLIC CellType ← Transistor[[mode:Depletion, strength:driveWeak]];
pE: PUBLIC CellType ← Transistor[[positive:FALSE]];
unE: PUBLIC CellType ← Transistor[[unidirectional:TRUE]];
unD: PUBLIC CellType ← Transistor[[mode:Depletion, strength:driveWeak, unidirectional:TRUE]];
upE: PUBLIC CellType ← Transistor[[positive:FALSE, unidirectional:TRUE]];
wpu: PUBLIC CellType ← Transistor[[strength:driveWeak, positive:FALSE, unidirectional:TRUE]];
wpd: PUBLIC CellType ← Transistor[[offStrength:driveWeak, unidirectional:TRUE, biased:TRUE]];
RegisterCells[];
END.