SwitchTest.Rose
Last Edited by: Spreitzer, May 2, 1985 1:17:49 pm PDT
Library Transistors;
CELLTYPE "SimpleInverter"
PORTS [in<BOOL, out>BOOL]
EVALSIMPLE
out ← NOT in;
ENDCELLTYPE;
CELLTYPE "SimpleNOR"
PORTS [in1, in2<BOOL, out>BOOL]
EVALSIMPLE
out ← NOT (in1 OR in2);
ENDCELLTYPE;
CELLTYPE "SwitchInverter"
PORTS [in<BIT, out>BIT, vdd, gnd<BIT]
EXPAND
pu: pE[in, vdd, out];
pd: nE[in, gnd, out]
ENDCELLTYPE;
CELLTYPE "Ringo"
PORTS [vdd, gnd, go<BOOL, r0, r1, r2, r3, r4>BOOL]
EXPAND
n0: SimpleNOR[go, r4, r0];
i1: SwitchInverter[r0, r1];
i2: SwitchInverter[r1, r2];
i3: SimpleInverter[r2, r3];
i4: SimpleInverter[r3, r4]
ENDCELLTYPE;
CELLTYPE "ThreeI"
PORTS [in<BOOL, out>BOOL, vdd, gnd<BOOL]
EXPAND
mid1, mid2: BOOL;
i1: SimpleInverter[in, mid1];
i2: SwitchInverter[mid1, mid2];
i3: SimpleInverter[mid2, out]
ENDCELLTYPE;
CELLTYPE "IPair"
PORTS [ipIn<Int[2], ipOut>Int[2], vdd, gnd<BOOL]
EXPAND
i0, i1, o0, o1: BOOL;
Equivalence ipIn, [i0, i1];
Equivalence [o0, o1], ipOut;
i0: SimpleInverter[i0, o0];
i1: SwitchInverter[i1, o1]
ENDCELLTYPE;
CELLTYPE "TwoBitBuffer"
PORTS [tbbIn<Int[2], tbbOut>Int[2]]
EVALSIMPLE
tbbOut ← tbbIn
ENDCELLTYPE;
CELLTYPE "SmAllTest"
PORTS [smIn0, smIn1<BOOL, smOut>Int[2], vdd, gnd<BOOL]
EXPAND
smIn, temp: Int[2];
tbb: TwoBitBuffer[smIn, temp];
ip: IPair[temp, smOut];
Equivalence smIn, [smIn0, smIn1]
ENDCELLTYPE