Latch.Rose
Last Edited by: Spreitzer, May 8, 1985 4:34:38 pm PDT
Last Edited by: Gasbarro, August 16, 1984 2:35:14 pm PDT
Library Transistors;
pu: Transistor[strength: driveWeak, positive: FALSE, unidirectional: TRUE];
CellType "InvertingLatch"
PORTS [clock<BIT, in<BIT, out>BIT, vdd, gnd<BIT, biasMinus<BIAS]
Expand
inl: BIT ←v "H";
t3: BIT;
latch: unE[gate: clock, ch1: in, ch2: inl];
pu1: upE[gate: inl, ch1: vdd, ch2: out];
pd1: unE[gate: inl, ch1: gnd, ch2: out];
pu2: pu[gate: out, ch1: vdd, ch2: inl];
pd2: Transistor[unidirectional: FALSE][gate: out, ch1: t3, ch2: inl];
bias: Transistor[offStrength: driveWeak, unidirectional: TRUE, biased: TRUE][gate: biasMinus, ch1: gnd, ch2: t3]
EndCellType