Library Transistors; CELLTYPE "SimpleInverter" PORTS [inBOOL] EVALSIMPLE out _ NOT in; ENDCELLTYPE; CELLTYPE "SimpleNOR" PORTS [in1, in2BOOL] EVALSIMPLE out _ NOT (in1 OR in2); ENDCELLTYPE; CELLTYPE "SwitchInverter" PORTS [inBIT, vdd, gndBOOL] EXPAND n0: SimpleNOR[go, r4, r0]; i1: SwitchInverter[r0, r1]; i2: SwitchInverter[r1, r2]; i3: SimpleInverter[r2, r3]; i4: SimpleInverter[r3, r4] ENDCELLTYPE; CELLTYPE "ThreeI" PORTS [inBOOL, vdd, gndInt[2], vdd, gndInt[2]] EVALSIMPLE tbbOut _ tbbIn ENDCELLTYPE; CELLTYPE "SmAllTest" PORTS [smIn0, smIn1Int[2], vdd, gnd