DIRECTORY Basics, IO, NumTypes, RoseCreate, RoseTypes, SwitchTypes; SimpleTest: CEDAR PROGRAM IMPORTS IO, NumTypes, RoseCreate ={OPEN RoseCreate, RoseTypes; bpw: NAT = Basics.bitsPerWord; bps: NAT = SwitchTypes.bitsPerSwitchVal; InverterSimpleIORef: TYPE = REF InverterSimpleIORec; InverterSimpleIORec: TYPE = RECORD [fil: [0 .. 16384) _ 0, in, out: BOOL]; InverterSwitchIORef: TYPE = REF InverterSwitchIORec; InverterSwitchIORec: TYPE = RECORD [in, out: SwitchTypes.SwitchVal]; InverterDriveRef: TYPE = REF InverterDriveRec; InverterDriveRec: TYPE = RECORD [ tag: DriveTagType, s: PACKED ARRAY InverterPort OF DriveLevel]; InverterPort: TYPE = MACHINE DEPENDENT {in, out, (3)}; CreateInverterIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {ioAsAny _ IF switch THEN NEW[InverterSwitchIORec] ELSE NEW[InverterSimpleIORec]}; CreateInverterDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {driveAsAny _ NEW[InverterDriveRec]}; InitializeInverter: PROC [cell: Cell] --Initializer-- = { drive: InverterDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny]; drive.s[in] _ ignore; drive.s[out] _ drive; }; EvalInverter: PROC [cell: Cell, perturb: PROC [portIndex: PortIndex]] --SimpleEval-- = { newIO: InverterSimpleIORef _ NARROW[cell.realCellStuff.newIO]; newIO.out _ NOT newIO.in; }; inverterPorts: Ports _ NEW [PortsRep[2]]; RegisterInverter: PROC = { inverterPorts[0] _ [ simple: [0, 14, 1], switch: [0, 0, bps], name: "in", type: NumTypes.boolType, input: TRUE]; inverterPorts[1] _ [ simple: [0, 15, 1], switch: [1, 0, bps], name: "out", type: NumTypes.boolType, output: TRUE]; [] _ RegisterCellType[ name: "Inverter", ioCreator: CreateInverterIO, driveCreator: CreateInverterDrive, initializer: InitializeInverter, evals: [EvalSimple: EvalInverter], ports: inverterPorts ]; }; DriverSimpleIORef: TYPE = REF DriverSimpleIORec; DriverSimpleIORec: TYPE = RECORD [ in, out: CARDINAL, str: [0 .. 16)]; DriverSwitchIORef: TYPE = REF DriverSwitchIORec; DriverSwitchIORec: TYPE = RECORD [ in, out: ARRAY [0 .. 16) OF SwitchTypes.SwitchVal, str: ARRAY [0 .. 4) OF SwitchTypes.SwitchVal]; DriverDriveRef: TYPE = REF DriverDriveRec; DriverDriveRec: TYPE = RECORD [ tag: DriveTagType, s: PACKED ARRAY DriverPort OF DriveLevel]; DriverPort: TYPE = MACHINE DEPENDENT {in, out, str, (3)}; CreateDriverIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] = {ioAsAny _ IF switch THEN NEW [DriverSwitchIORec] ELSE NEW [DriverSimpleIORec]}; CreateDriverDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] = {driveAsAny _ NEW [DriverDriveRec]}; EvalDriver: PROC [cell: Cell, perturb: PROC [portIndex: PortIndex]] --SimpleEval-- = { io: DriverSimpleIORef _ NARROW[cell.realCellStuff.newIO]; drive: DriverDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny]; drive.s[out] _ VAL[io.str]; io.out _ io.in; }; driverPorts: Ports _ NEW [PortsRep[3]]; RegisterDriver: PROC = { driverPorts[0] _ [ simple: [0, 0, 1*bpw], switch: [0, 0, 16*bpw], name: "in", type: NumTypes.NumType[16], input: TRUE ]; driverPorts[1] _ [ simple: [1, 0, 1*bpw], switch: [16, 0, 16*bpw], name: "out", type: NumTypes.NumType[16], output: TRUE ]; driverPorts[2] _ [ simple: [2, 12, 4], switch: [32, 0, 4*bpw], name: "str", type: NumTypes.NumType[4], input: TRUE ]; [] _ RegisterCellType[ name: "Driver", ioCreator: CreateDriverIO, driveCreator: CreateDriverDrive, evals: [EvalSimple: EvalDriver], ports: driverPorts ]; }; IncrementerSimpleIORef: TYPE = REF IncrementerSimpleIORec; IncrementerSimpleIORec: TYPE = RECORD [ in, out: CARDINAL]; IncrementerSwitchIORef: TYPE = REF IncrementerSwitchIORec; IncrementerSwitchIORec: TYPE = RECORD [ in, out: ARRAY [0 .. 16) OF SwitchTypes.SwitchVal]; IncrementerDriveRef: TYPE = REF IncrementerDriveRec; IncrementerDriveRec: TYPE = RECORD [ tag: DriveTagType, s: PACKED ARRAY IncrementerPort OF DriveLevel]; IncrementerPort: TYPE = MACHINE DEPENDENT {in, out, (3)}; CreateIncrementerIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] = {ioAsAny _ IF switch THEN NEW [IncrementerSwitchIORec] ELSE NEW [IncrementerSimpleIORec]}; CreateIncrementerDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] = {driveAsAny _ NEW [IncrementerDriveRec]}; EvalIncrementer: PROC [cell: Cell, perturb: PROC [portIndex: PortIndex]] --SimpleEval-- = { io: IncrementerSimpleIORef _ NARROW[cell.realCellStuff.newIO]; drive: IncrementerDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny]; io.out _ io.in + 1; }; incrementerPorts: Ports _ NEW [PortsRep[2]]; RegisterIncrementer: PROC = { incrementerPorts[0] _ [ simple: [0, 0, 1*bpw], switch: [0, 0, 16*bpw], name: "in", type: NumTypes.NumType[16], input: TRUE ]; incrementerPorts[1] _ [ simple: [1, 0, 1*bpw], switch: [16, 0, 16*bpw], name: "out", type: NumTypes.NumType[16], output: TRUE ]; [] _ RegisterCellType[ name: "Incrementer", ioCreator: CreateIncrementerIO, driveCreator: CreateIncrementerDrive, evals: [EvalSimple: EvalIncrementer], ports: incrementerPorts ]; }; ExpandContest: PROC [thisCell: Cell, to: ExpansionReceiver] = { contestants: REF NAT _ NARROW[thisCell.type.typeData]; [] _ to.class.NodeInstance[ erInstance: to.instance, name: "outcome", type: NumTypes.NumType[16]]; FOR i: NAT IN [0 .. contestants^) DO [] _ to.class.CellInstance[ erInstance: to.instance, instanceName: IO.PutFR["d[%g]", IO.int[i]], typeName: "Driver", interfaceNodes: IO.PutFR["in: c[%g].in, out: outcome, str: c[%g].str", IO.int[i], IO.int[i]] ]; ENDLOOP; [] _ to.class.CellInstance[ erInstance: to.instance, instanceName: "inc", typeName: "Incrementer", interfaceNodes: "in: outcome, out: incedOutcome" ]; }; RegisterContest: PROC [contestants: NAT] = { contestPorts: Ports _ NEW [PortsRep[contestants*2+1]]; FOR i: NAT IN [0 .. contestants) DO contestPorts[2*i] _ [ simple: noField, switch: noField, name: IO.PutFR["c[%g].in", IO.int[i]], type: NumTypes.NumType[16], input: TRUE]; contestPorts[2*i+1] _ [ simple: noField, switch: noField, name: IO.PutFR["c[%g].str", IO.int[i]], type: NumTypes.NumType[4], input: TRUE]; ENDLOOP; contestPorts[2*contestants] _ [ simple: noField, switch: noField, name: "incedOutcome", type: NumTypes.NumType[16], output: TRUE]; [] _ RegisterCellType[ name: IO.PutFR["Contest[%g]", IO.int[contestants]], expandProc: ExpandContest, ports: contestPorts, typeData: NEW [NAT _ contestants] ]; }; RegisterInverter[]; RegisterDriver[]; RegisterIncrementer[]; RegisterContest[3]; }. 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