Library Transistors;Imports IO, Transistors;CELLTYPE "UnaryCounter"PORTS [load, shift<BOOL, out>Int[4]]InittableStatecur, next: [0 ..4) _ 0EvalSimpleIF load THEN next _ (cur + 1) MOD 4;IF shift THEN out _ selected[cur _ next];ENDCELLTYPE;CEDARselected: ARRAY [0 .. 4) OF [0 .. 16) = [8, 4, 2, 1];;CELLTYPE "Downer"PORTS [vdd, gnd, pc, go<BIT, in<Int[4], downed>Switch[4]]EXPANDin0, in1, in2, in3, downed0, downed1, downed2, downed3, mid0, mid1, mid2, mid3: BIT;Equivalence [in0, in1, in2, in3], in;Equivalence [downed0, downed1, downed2, downed3], downed;CEDARFOR i: INT IN [0 .. 4) DO[] _ to.class.CellInstance[erInstance: to.instance,instanceName: IO.PutFR["down%gA", IO.int[i]],typeName: Transistors.nE.name,interfaceNodes: IO.PutFR["gate: go, ch1: mid%g, ch2: gnd", IO.int[i]]];[] _ to.class.CellInstance[erInstance: to.instance,instanceName: IO.PutFR["down%gB", IO.int[i]],typeName: Transistors.nE.name,interfaceNodes: IO.PutFR["gate: in%g, ch1: mid%g, ch2: downed%g", IO.int[i], IO.int[i], IO.int[i]]];ENDLOOP;ENDCELLTYPE;CELLTYPE "BarrellShifter"PORTS [vdd, gnd, pc, go<BOOL, shift, in<Switch[4], out>Switch[4]]Expandin0, in1, in2, in3, out0, out1, out2, out3, shift0, shift1, shift2, shift3: BIT;Equivalence [in0, in1, in2, in3], in;Equivalence [out0, out1, out2, out3], out;Equivalence [shift0, shift1, shift2, shift3], shift;CEDARFOR i: INT IN [0 .. 4) DO[] _ to.class.CellInstance[erInstance: to.instance,instanceName: IO.PutFR["pcIn%g", IO.int[i]],typeName: Transistors.nE.name,interfaceNodes: IO.PutFR["gate: pc, ch1: in%g, ch2: vdd", IO.int[i]]];[] _ to.class.CellInstance[erInstance: to.instance,instanceName: IO.PutFR["pcOut%g", IO.int[i]],typeName: Transistors.nE.name,interfaceNodes: IO.PutFR["gate: pc, ch1: out%g, ch2: vdd", IO.int[i]]];FOR j: INT IN [0 .. 4) DO[] _ to.class.CellInstance[erInstance: to.instance,instanceName: IO.PutFR["bs%g-%g", IO.int[i], IO.int[j]],typeName: Transistors.nE.name,interfaceNodes: IO.PutFR["gate: shift%g, ch1: in%g, ch2: out%g", IO.int[(j + 4 - i) MOD 4], IO.int[i], IO.int[j]]];ENDLOOP;ENDLOOP;ENDCELLTYPE;CELLTYPE "BSTest"PORTS [vdd, gnd, pc, go<BIT, d1, d2<Int[4], ans>Switch[4]]ExpandbsIn, shift: Switch[4];uc: UnaryCounter[go, pc, shift];dr1: Downer[in: d1, downed: bsIn];dr2: Downer[in: d2, downed: ans];bs: BarrellShifter[in: bsIn, out: ans]ENDCELLTYPE    L  MessyTest.RoseLast Edited by: Spreitzer, May 2, 1985 2:51:34 pm PDT ÊÛ  ˜ J™J™5J˜ Jšœ˜JšœÏkœ˜J˜ šœ˜Jšœœ˜$˜J˜—˜
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