<> <> <> Imports IO, RoseRun, RoseClocks, SRHC; Directory ShiftOps; Library RoseClocks, SRHC; SRWC: LAMBDA [s1, s2: |[0 .. 16)|] RETURN CELLTYPE AutoName PORTS [phi1, phi2<, inputINT[4]] Assert ((EC "Structure" "SRWC") (Zwop 42)) Expand middle: INT[4]-(Frobnicate)-(Lurbism "arffle" 4.7); First: SRHC[s1][input:input, clock:phi1, output:middle]-(Glozzle 3); second: SRHC[s2][input:middle, clock:phi2--, output: output--] ENDCELLTYPE; NBitSR: LAMBDA [n: |NAT|] RETURN CELLTYPE AutoName PORTS [phi1, phi2<, inputINT[4]] Expand CEDAR prev, next: ROPE; next _ "input"; FOR i: CARDINAL IN [0..n) DO prev _ next; IF n # i+1 THEN BEGIN next _ IO.PutFR["node%g", IO.card[i+1]]; [] _ to.class.NodeInstance[erInstance: to.instance, name: next, type: NumTypes.NumType[4]]; END ELSE next _ "output"; [] _ to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["SRWC%g", IO.card[i]], typeName: SRWC[[13, 7]].name, interfaceNodes: IO.PutFR["input: %g, phi2: phi2, output: %g", IO.rope[prev], IO.rope[next]]]; ENDLOOP; Test T BlackBox scramble: ARRAY [0 .. 16) OF [0 .. 16) = [ 0, 1, 3, 6, 10, 15, 5, 12, 4, 13, 7, 2, 14, 11, 9, 8]; drive[phi1] _ drive[phi2] _ drive[input] _ drive; drive[output] _ test; phi1 _ TRUE; phi2 _ TRUE; FOR i: [0 .. 16) IN [0 .. 16) DO output _ input _ i; [] _ RoseRun.Eval[handle]; ENDLOOP; phi1 _ FALSE; phi2 _ FALSE; [] _ RoseRun.Eval[handle]; FOR i: INTEGER IN [0 .. 32+2*n] DO Clockit: PROC = { phi1 _ TRUE; [] _ RoseRun.Eval[handle]; phi1 _ FALSE; [] _ RoseRun.Eval[handle]; input _ scramble[i MOD 16]; output _ (IF i < n THEN 15 ELSE scramble[(i-n) MOD 16]); phi2 _ TRUE; [] _ RoseRun.Eval[handle]; phi2 _ FALSE; [] _ RoseRun.Eval[handle]; }; Clockit[]; ENDLOOP; ENDCELLTYPE; CELLTYPE "Fooey" ENDCELLTYPE; CELLTYPE "Counter" PORTS [phi1, phi2<, count>INT[4], report=EnumType["ShiftOps.ShiftOp"]] InittableState next: [0..16) _ 5 EvalSimple IF phi1 THEN next _ (count + 1) MOD 16; IF phi2 THEN count _ next; report _ reports[phi1][phi2]; ENDCELLTYPE; CEDAR reports: ARRAY BOOLEAN OF ARRAY BOOLEAN OF ShiftOps.ShiftOp _ [[BothOff, Storing], [Looking, BothOn]]; ; TopNBitSR: LAMBDA [n: |CARDINAL|] RETURN CELLTYPE AutoName PORTS [] Expand front, back: INT[4]; PhaseA, clk2: BOOL _v "FALSE"; sink: EnumType["ShiftOps.ShiftOp"]; clkGen: ClockGen[][PhaseA: PhaseA, PhaseB: clk2]; cntr: Counter[phi1: PhaseA, phi2: clk2, count: front, report: sink]; shifter: NBitSR[n][input: front, output: back, phi1: PhaseA, phi2: clk2] ENDCELLTYPE