<> <> Library RoseClocks; CELLTYPE CardCounter PORTS [PhaseA, PhaseBINT[16]] InittableStateFields next: CARDINAL _ 7 EvalSimple IF PhaseA THEN next _ next + 1; IF PhaseB THEN count _ next; ENDCELLTYPE; Modulator: LAMBDA [modulus: |INTEGER|] RETURN CELLTYPE AutoName PORTS [count< INT[16], ans>INT[16]] EvalSimple IF (count MOD modulus) = 0 THEN ans _ count ENDCELLTYPE; CELLTYPE RoseTest3 Expand PhaseA, PhaseB: BOOL; count, ans: INT[16]; clkGen: ClockGen[]; counter: CardCounter[]; mod3: Modulator[3][]; mod5: Modulator[3][] ENDCELLTYPE