<> <> <> Imports BiasTypes; Library Latch, RoseClocks; CellType "LatchTest" Expand n0, n1, n2, n3: BIT _v "L"; gnd: BIT _v "L" _d |SwitchTypes.refInput|; vdd: BIT _v "H" _d |SwitchTypes.refInput|; biasMinus: BIAS _v "-"; ph1, ph2: BIT; cg: ClockGen[][ph1, ph2]; l0: InvertingLatch[ph1, n0, n1]; l1: InvertingLatch[ph2, n1, n2]; l2: InvertingLatch[ph1, n2, n3]; l3: InvertingLatch[ph2, n3, n0] EndCellType