<> <> Library Transistors; Imports SwitchTypes; CELLTYPE "EPInverter" PORTS [inputBOOL] EvalSimple output _ NOT input ENDCELLTYPE; CELLTYPE "PassBlock" PORTS [input < INT[4], gate < BOOL, output> INT[4]] EvalSimple IF gate THEN output _ input; Expand i0, i1, i2, i3, o0, o1, o2, o3: BOOL _d |SwitchTypes.refChargeWeak|; p0: unE[gate, i0, o0]; p1: unE[gate, i1, o1]; p2: unE[gate, i2, o2]; p3: unE[gate, i3, o3]; Equivalence [i0, i1, i2, i3], input; Equivalence output, [o0, o1, o2, o3] ENDCELLTYPE; CELLTYPE "InvertBlock" PORTS [input< INT[4], output> INT[4]] EvalSimple output _ 15 - input; Expand i0, i1, i2, i3, o0, o1, o2, o3: BOOL _d |SwitchTypes.refChargeWeak|; ir0: EPInverter[i0, o0]; ir1: EPInverter[i1, o1]; ir2: EPInverter[i2, o2]; ir3: EPInverter[i3, o3]; Equivalence [i0, i1, i2, i3], input; Equivalence output, [o0, o1, o2, o3] ENDCELLTYPE