Library Transistors; Imports IO, NumTypes, RoseTypes, SwitchTypes, Transistors; CELLTYPE "PassBlock" PORTS [input < INT[4], gate < BOOL, output> INT[4]] EvalSimple IF gate THEN output _ input; Expand sGate: BIT; CEDAR in, out, sin, sout: ARRAY [0 .. 4) OF Node; ins, outs: StretchList _ NIL; FOR i: NAT DECREASING IN [0 .. 4) DO in[i] _ to.class.NodeInstance[erInstance: to.instance, name: IO.PutFR["in[%g]", IO.card[i]], type: NumTypes.boolType]; out[i] _ to.class.NodeInstance[erInstance: to.instance, name: IO.PutFR["out[%g]", IO.card[i]], type: NumTypes.boolType]; sin[i] _ to.class.NodeInstance[erInstance: to.instance, name: IO.PutFR["sin[%g]", IO.card[i]], type: SwitchTypes.bitType]; sout[i] _ to.class.NodeInstance[erInstance: to.instance, name: IO.PutFR["sout[%g]", IO.card[i]], type: SwitchTypes.bitType]; ins _ CONS[Single[in[i]], ins]; outs _ CONS[Single[out[i]], outs]; [] _ to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["pass[%g]", IO.card[i]], typeName: Transistors.unE.name, interfaceNodes: IO.PutFR["sGate, sin[%g], sout[%g]", IO.card[i], IO.card[i]]]; [] _ to.class.ChangeReps[erInstance: to.instance, a: in[i], b: sin[i], writeA: FALSE, writeB: TRUE]; [] _ to.class.ChangeReps[erInstance: to.instance, a: out[i], b: sout[i], writeA: TRUE, writeB: FALSE]; ENDLOOP; [] _ to.class.ChangeReps[erInstance: to.instance, a: gate, b: sGate, writeA: FALSE, writeB: TRUE]; to.class.SplitJoin[erInstance: to.instance, a: LIST[Sub[input]], b: ins, writeA: FALSE, writeB: TRUE]; to.class.SplitJoin[erInstance: to.instance, a: LIST[Sub[output]], b: outs, writeA: TRUE, writeB: FALSE]; ENDCELLTYPE; CELLTYPE "InvertBlock" PORTS [input< INT[4], output> INT[4]] EvalSimple output _ 15 - input; Expand CEDAR in, out: ARRAY [0 .. 4) OF Node; ins, outs: StretchList _ NIL; FOR i: NAT DECREASING IN [0 .. 4) DO in[i] _ to.class.NodeInstance[erInstance: to.instance, name: IO.PutFR["in[%g]", IO.card[i]], type: NumTypes.boolType]; out[i] _ to.class.NodeInstance[erInstance: to.instance, name: IO.PutFR["out[%g]", IO.card[i]], type: NumTypes.boolType]; ins _ CONS[Single[in[i]], ins]; outs _ CONS[Single[out[i]], outs]; [] _ to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["inv[%g]", IO.card[i]], typeName: "EPInverter", interfaceNodes: IO.PutFR["in[%g], out[%g]", IO.card[i], IO.card[i]]]; ENDLOOP; to.class.SplitJoin[erInstance: to.instance, a: LIST[Sub[input]], b: ins, writeA: FALSE, writeB: TRUE]; to.class.SplitJoin[erInstance: to.instance, a: LIST[Sub[output]], b: outs, writeA: TRUE, writeB: FALSE]; ENDCELLTYPE; CELLTYPE "EPInverter" PORTS [inputBOOL] EvalSimple output _ NOT input ENDCELLTYPE XExamplePrimitives.Rose Last Edited by: Spreitzer, October 9, 1984 10:11:39 pm PDT สม– "cedar" style˜Icode™K™:K˜K˜Kšœฯkœ0˜:K˜šœฯb œ˜Kšœ œ œ œ˜3˜ Kšœœ˜—˜Kšœœ˜ š˜Kšœœ œ˜+Kšœœ˜š œœ œœ ˜$Kšœ=œœ$˜vKšœ>œœ$˜xKšœ>œœ&˜zKšœ?œœ&˜|Kšœœ˜Kšœœ˜"Kš œBœœ;œ#œ œ ˜าKšœOœ œ˜dKšœQœ œ˜fKšœ˜—KšœMœ œ˜bKšœ/œœ œ˜fKšœ/œ œ œ˜h——Kš œ˜ —K˜šœž œ˜Kšœ œ œ˜%˜ K˜—˜š˜Kšœ œ œ˜ Kšœœ˜š œœ œœ ˜$Kšœ=œœ$˜vKšœ>œœ$˜xKšœœ˜Kšœœ˜"Kš œBœœ3œœ œ ˜ภKšœ˜—Kšœ/œœ œ˜fKšœ/œ œ œ˜h——Kš œ˜ —K˜šœž œ˜Kšœœ œ˜˜ Kšœ œ˜—Kš ˜ ——…— j ƒ