Transistors.Mesa
created by RoseTranslate from Transistors.Rose of October 9, 1984 4:17:13 pm PDT for Spreitzer.pa at December 2, 1984 4:49:31 pm PST
DIRECTORY
RoseTypes, RoseCreate, Asserting, BiasTypes, RoseRun, SwitchTypes, PrintTV, AMBridge, IO;
Transistors: CEDAR PROGRAM
IMPORTS RoseCreate, Asserting, BiasTypes, RoseRun, RoseTypes, SwitchTypes, PrintTV, AMBridge, IO =
BEGIN OPEN
RoseTypes, SwitchTypes, RoseRun, RoseCreate;
Signal Type decls
RegisterCells: PROC =
BEGIN
END;
otherss: SymbolTable ← RoseCreate.GetOtherss["Transistors.pass"];
explicitly requested CEDAR:
Mode: PUBLIC TYPE = {Enhancement, Depletion};
Conductance: TYPE = {Off, On, Indeterminate};
ComputeState: ARRAY Mode OF ARRAY BOOL--positive-- OF ARRAY Level OF Conductance = [
Enhancement: [[On, Off, Indeterminate], [Off, On, Indeterminate]],
Depletion: [ALL[On], ALL[On]]];
Gate: TYPE = RECORD [variant: SELECT COMPUTED BOOL--biased-- FROM
FALSE => [switch: SwitchVal],
TRUE => [bh: BiasTypes.BiasHolder],
ENDCASE];
SG: TYPE = Gate[FALSE];
BG: TYPE = Gate[TRUE];
TransIORef: TYPE = REF TransIORec;
TransIORec: TYPE = MACHINE DEPENDENT RECORD [
gate(0:0..15): Gate,
fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
ch1(1:16-bitsPerSwitchVal..15): SwitchVal,
fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
ch2(2:16-bitsPerSwitchVal..15): SwitchVal];
BiasToLevel: ARRAY BiasTypes.Bias OF Level = [H, L];
classes: ARRAY --positive--BOOL OF ARRAY Mode OF ROPE ← [
FALSE: [Enhancement: "pE", Depletion: "pD"],
TRUE: [Enhancement: "nE", Depletion: "nD"]];
TransistorArgs: PUBLIC TYPE = RECORD [
strength: Strength ← drive,
positive: BOOL ← TRUE,
mode: Mode ← Enhancement,
unidirectional: BOOL ← FALSE,
biased: BOOL ← FALSE,
offStrength: Strength ← none];
OldTransistor: TYPE = RECORD [args: TransistorArgs, ct: CellType];
oldTransistor: LIST OF OldTransistor ← NIL;
Transistor: PUBLIC PROC [args: TransistorArgs] RETURNS [ct: CellType] =
BEGIN
FOR old: LIST OF OldTransistor ← oldTransistor, old.rest WHILE old # NIL DO
IF old.first.args = args THEN RETURN [old.first.ct]
ENDLOOP;
ct ← RoseCreate.RegisterCellType[name: TransistorName[args],
expandProc: NIL,
ioCreator: CreateTransistorIO, initializer: InitializeTransistor,
evals: [ValsChanged: TransistorValsChanged, PropQ: TransistorPropQ, InitUD: TransistorInitUD, PropUD: TransistorPropUD, FinalUD: TransistorFinalUD, EvalSimple: TransistorEvalSimple, FindVicinity: TransistorFindVicinity],
blackBox: NIL, stateToo: NIL,
ports: CreateTransistorPorts[args],
drivePrototype: NIL,
typeData: NEW [TransistorArgs ← args],
other: InitialTransistorProps[args]];
oldTransistor ← CONS[[args, ct], oldTransistor];
END;
TransistorName: PROC [args: TransistorArgs] RETURNS [name: ROPE] = {
to: IO.STREAM ← IO.ROS[]; to.PutRope["Transistor"];
TRUSTED {PrintTV.Print[tv: AMBridge.TVForReferent[NEW [TransistorArgs ← args]], put: to]};
name ← IO.RopeFromROS[to]};
CreateTransistorIO: PROC [cell: Cell] --IOCreator-- = {args: REF TransistorArgs ← NARROW[cell.type.typeData]; {OPEN args;
cell.realCellStuff.newIO ← NEW [TransIORec];
cell.realCellStuff.oldIO ← NEW [TransIORec];
cell.realCellStuff.switchIO ← NEW [TransIORec];
}};
CreateTransistorPorts: PROC [args: TransistorArgs] RETURNS [ports: Ports] =
BEGIN OPEN args;
ports ← NEW [PortsRep[3]];
ports[0] ← [0, 1, "gate", IF biased THEN BiasTypes.biasType ELSE bitType, TRUE, FALSE];
IF unidirectional
THEN {
ports[1] ← [1, 1, "ch1", bitType, TRUE, FALSE];
ports[2] ← [2, 1, "ch2", bitType, FALSE, TRUE];
}
ELSE {
ports[1] ← [1, 1, "ch1", bitType, TRUE, TRUE];
ports[2] ← [2, 1, "ch2", bitType, TRUE, TRUE];
ports[1].other ← Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[1].other];
ports[2].other ← Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[2].other];
};
END;
TransistorStateRef: TYPE = REF TransistorStateRec;
TransistorStateRec: TYPE = RECORD [
conductance: Conductance
];
InitializeTransistor: Initializer = {
IF leafily THEN
BEGIN
ioRec: TransIORef ← NARROW[cell.realCellStuff.newIO];
args: REF TransistorArgs ← NARROW [cell.type.typeData];
state: TransistorStateRef ← NEW [TransistorStateRec];
cell.realCellStuff.state ← state;
BEGIN OPEN ioRec, state, args;
conductance ← SELECT mode FROM Enhancement => Indeterminate, Depletion => On, ENDCASE => ERROR;
conductance ← ComputeState[mode][positive][WITH g: gate SELECT biased FROM FALSE => g.switch.val, TRUE => BiasToLevel[g.bh.bias], ENDCASE => ERROR];
END;
END;
};
TransistorValsChanged: CellProc =
BEGIN
sw: TransIORef ← NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
IF mode = Enhancement AND NOT biased THEN {
new: Conductance ← ComputeState[mode][positive][WITH g: gate SELECT biased FROM FALSE => g.switch.val, TRUE => BiasToLevel[g.bh.bias], ENDCASE => ERROR];
IF new # conductance THEN {
conductance ← new;
IF NOT unidirectional THEN PerturbPort[cell, 1];
PerturbPort[cell, 2];
}
};
END;
END;
TransistorPropQ: CellProc =
BEGIN
sw: TransIORef ← NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On => strength,
Off, Indeterminate => offStrength,
ENDCASE => ERROR;
IF cs > none THEN {
IF unidirectional THEN NULL ELSE
ch1.s[q] ← MAX[ch1.s[q], MIN[cs, ch2.s[q]]];
ch2.s[q] ← MAX[ch2.s[q], MIN[cs, ch1.s[q]]];
};
END;
END;
TransistorInitUD: CellProc =
BEGIN
sw: TransIORef ← NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On => strength,
Off, Indeterminate => offStrength,
ENDCASE => ERROR;
IF unidirectional AND ch1.s[q] < MIN[cs, ch2.s[q]] THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
END;
END;
TransistorPropUD: CellProc =
BEGIN
sw: TransIORef ← NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On, Indeterminate => strength,
Off => offStrength,
ENDCASE => ERROR;
IF cs > none THEN {
IF unidirectional THEN NULL
ELSE {
ch1.s[u] ← MAX[ch1.s[u], MIN[cs, ch2.s[u]]];
ch1.s[d] ← MAX[ch1.s[d], MIN[cs, ch2.s[d]]];
};
ch2.s[u] ← MAX[ch2.s[u], MIN[cs, ch1.s[u]]];
ch2.s[d] ← MAX[ch2.s[d], MIN[cs, ch1.s[d]]];
};
END;
END;
TransistorFinalUD: CellProc =
BEGIN
sw: TransIORef ← NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On, Indeterminate => strength,
Off => offStrength,
ENDCASE => ERROR;
IF cs > none AND unidirectional THEN {
IF ch1.s[u] < Block[MIN[cs, ch2.s[u]], ch1.s[q]] THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
IF ch1.s[d] < Block[MIN[cs, ch2.s[d]], ch1.s[q]] THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
};
END;
END;
TransistorEvalSimple: CellProc =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, args, state;
IF mode = Enhancement AND biased THEN {
new: Conductance ← ComputeState[mode][positive][WITH g: gate SELECT biased FROM FALSE => g.switch.val, TRUE => BiasToLevel[g.bh.bias], ENDCASE => ERROR];
IF new # conductance THEN {
conductance ← new;
IF NOT unidirectional THEN PerturbPort[cell, 1];
PerturbPort[cell, 2];
}
};
END;
END;
TransistorFindVicinity: PROC [cell: Cell, portIndex: CARDINAL, evenIfInput: BOOL ← FALSE] =
BEGIN
args: REF TransistorArgs ← NARROW[cell.type.typeData];
newIO: TransIORef ← NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN args, state;
NotOff: PROC RETURNS [no: BOOL] = INLINE {
no ← SELECT conductance FROM
On, Indeterminate => TRUE,
Off => offStrength > none,
ENDCASE => ERROR};
SELECT portIndex FROM
0 => NULL;
1, 2 => IF NotOff[] THEN FindExteriorVicinity[cell, 3-portIndex];
ENDCASE => ERROR;
END;
END;
InitialTransistorProps: PROC [args: TransistorArgs] RETURNS [other: Assertions] = {
other ← NIL;
--designer's part: --{OPEN args;
other ← Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], classes[positive][mode]], inAdditionTo: other];
};
};
nE: PUBLIC CellType ← Transistor[[]];
nD: PUBLIC CellType ← Transistor[[mode:Depletion, strength:driveWeak]];
pE: PUBLIC CellType ← Transistor[[positive:FALSE]];
unE: PUBLIC CellType ← Transistor[[unidirectional:TRUE]];
unD: PUBLIC CellType ← Transistor[[mode:Depletion, strength:driveWeak, unidirectional:TRUE]];
upE: PUBLIC CellType ← Transistor[[positive:FALSE, unidirectional:TRUE]];
wpu: PUBLIC CellType ← Transistor[[strength:driveWeak, positive:FALSE, unidirectional:TRUE]];
wpd: PUBLIC CellType ← Transistor[[offStrength:driveWeak, unidirectional:TRUE, biased:TRUE]];
RegisterCells[];
END.