<> <> Directory SwitchTypes; Imports RoseRun; Library Transistors; CellType "Test2BInverter" Ports [inBIT-(XPhillic), gnd, vdd= d <<-2.5: strongly driven low>> <<-1.5: weakly driven low>> <<-0.5: charged low>> <<+0.5: charged high>> <<+1.5: weakly driven high>> <<+2.5: strongly driven high>> PastStrong: NAT = 3; TweenStrongAndWeak: NAT = 2; TweenWeakAndChage: NAT = 1; LevelFromSignal: PROC [s: Signal] RETURNS [l: Level] = { IF SGN[s.d] * SGN[s.u] < 0 THEN RETURN [X]; l _ SELECT SGN[s.d] + SGN[s.u] FROM < 0 => L, > 0 => H, ENDCASE => ERROR; }; Mux: PROC [a, b: Signal] RETURNS [c: Signal] = { Try: PROC [s1, s2: Signal] RETURNS [worked: BOOL] = { sgn1: INTEGER _ SGN[s1.d] + SGN[s1.u]; worked _ FALSE; IF sgn1 = 0 THEN RETURN [FALSE]; IF SGN[s2.d] * sgn1 >= 0 AND SGN[s2.u] * sgn1 >= 0 THEN { SELECT sgn1 FROM > 0 => c _ [d: MAX[s1.d, s2.d], u: MAX[s1.u, s2.u]]; < 0 => c _ [d: MIN[s1.d, s2.d], u: MIN[s1.u, s2.u]]; ENDCASE => ERROR; RETURN [TRUE]}; SELECT sgn1 FROM > 0 => worked _ s1.d >= -s2.d; < 0 => worked _ s1.u <= -s2.u; ENDCASE => ERROR; IF worked THEN c _ s1}; IF Try[a, b] THEN RETURN; IF Try[b, a] THEN RETURN; c _ [d: MIN[a.d, b.d], u: MAX[a.u, b.u]]; }; MaxPos: PROC [s: Signal] RETURNS [mp: NAT] = {mp _ MAX[ABS[s.d], ABS[s.u]]}; Charge: PROC [s: Signal] RETURNS [t: Signal] = {t _ [d: MAX[-1, MIN[s.d, 0]], u: MIN[1, MAX[s.u, 0]]]}; Limit: PROC [l: Level, s: Signal] RETURNS [t: Signal] = { t _ SELECT l FROM L => [0, 0], H => s, X => [d: MIN[s.d, 0], u: MAX[s.u, 0]], ENDCASE => ERROR; }; Not: ARRAY Level OF Signal = [ H: [-PastStrong, -TweenStrongAndWeak], X: [-PastStrong, TweenStrongAndWeak], L: [TweenWeakAndChage, TweenStrongAndWeak]]; SVFromLevel: PROC [l: Level] RETURNS [sv: SwitchTypes.SwitchVal] = { sv _ [ s: [ q: input, u: IF l = L THEN none ELSE input, d: IF l = H THEN none ELSE input], val: l]; }; SGN: PROC [x: INT] RETURNS [s: [-1 .. 1]] = { s _ SELECT x FROM < 0 => -1, = 0 => 0, > 0 => 1, ENDCASE => ERROR; };