RoseTest.Mesa
Last Edited by: Spreitzer, October 6, 1984 5:38:01 pm PDT
DIRECTORY RoseCreate, RoseTypes, SwitchTypes, Transistors;
RoseTest:
CEDAR
PROGRAM
IMPORTS RoseCreate, SwitchTypes, Transistors =
BEGIN OPEN SwitchTypes, RoseCreate, RoseTypes;
nE: ROPE ← Transistors.Transistor[[]].name;
nD: ROPE ← Transistors.Transistor[[driveWeak, TRUE, Depletion]].name;
ExpandTest1:
PROC [thisCell: Cell, to: ExpansionReceiver]
--ExpandProc-- =
BEGIN
vdd: Node ← to.class.NodeInstance[to.instance, "vdd", bitType, "H", refInput];
gnd: Node ← to.class.NodeInstance[to.instance, "gnd", bitType, "L", refInput];
in: Node ← to.class.NodeInstance[to.instance, "in", bitType];
out: Node ← to.class.NodeInstance[to.instance, "out", bitType];
pd: Cell ← to.class.CellInstance[to.instance, "pd", nE, "in, gnd, out"];
pu: Cell ← to.class.CellInstance[to.instance, "pu", nD, "out, vdd, out"];
END;
InterterIORef: TYPE = REF InverterIORec;
InverterIORec:
TYPE =
MACHINE
DEPENDENT
RECORD [
fill0(0:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
vdd(0:16-bitsPerSwitchVal..15): SwitchVal,
fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
gnd(1:16-bitsPerSwitchVal..15): SwitchVal,
fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
in(2:16-bitsPerSwitchVal..15): SwitchVal,
fill3(3:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
out(3:16-bitsPerSwitchVal..15): SwitchVal];
inverterPorts: Ports ← NEW [PortsRep[4]];
CreateInverterIO: IOCreator
--PROC [cell: Cell, initData: REF ANY]-- =
BEGIN
cell.realCellStuff.newIO ← NEW [InverterIORec];
cell.realCellStuff.oldIO ← NEW [InverterIORec];
END;
pass: ROPE ← Transistors.Transistor[[drive, TRUE, Enhancement, TRUE]].name;
pullup: ROPE ← Transistors.Transistor[[driveWeak, TRUE, Depletion, TRUE]].name;
ExpandInverter:
PROC [thisCell: Cell, to: ExpansionReceiver]
--ExpandProc-- =
BEGIN
pd: Cell ← to.class.CellInstance[to.instance, "pd", pass, "in, gnd, out"];
pu: Cell ← to.class.CellInstance[to.instance, "pu", pullup, "out, vdd, out"];
END;
ExpandTest2:
PROC [thisCell: Cell, to: ExpansionReceiver]
--ExpandProc-- =
BEGIN
vdd: Node ← to.class.NodeInstance[to.instance, "vdd", bitType, "H", refInput];
gnd: Node ← to.class.NodeInstance[to.instance, "gnd", bitType, "L", refInput];
in1: Node ← to.class.NodeInstance[to.instance, "in1", bitType, NIL, refInput];
in2: Node ← to.class.NodeInstance[to.instance, "in2", bitType, NIL, refInput];
out1: Node ← to.class.NodeInstance[to.instance, "out1", bitType];
out2: Node ← to.class.NodeInstance[to.instance, "out2", bitType];
sel1: Node ← to.class.NodeInstance[to.instance, "sel1", bitType, NIL, refInput];
sel2: Node ← to.class.NodeInstance[to.instance, "sel2", bitType, NIL, refInput];
ans: Node ← to.class.NodeInstance[to.instance, "ans", bitType];
inv1: Cell ← to.class.CellInstance[to.instance, "inv1", "Inverter", "in: in1, out: out1"];
inv2: Cell ← to.class.CellInstance[to.instance, "inv2", "Inverter", "in: in2, out: out2"];
pass1: Cell ← to.class.CellInstance[to.instance, "pass1", nE, "sel1, out1, ans"];
pass2: Cell ← to.class.CellInstance[to.instance, "pass2", nE, "sel2, out2, ans"];
END;
Setup:
PROC =
BEGIN
[] ← RegisterCellType[
name: "Test1",
expandProc: ExpandTest1,
evals: [],
ports: NEW [PortsRep[0]]
];
inverterPorts[0] ← [0, 1, "vdd", bitType, TRUE, FALSE];
inverterPorts[1] ← [1, 1, "gnd", bitType, TRUE, FALSE];
inverterPorts[2] ← [2, 1, "in", bitType, TRUE, FALSE];
inverterPorts[3] ← [3, 1, "out", bitType, TRUE, TRUE];
[] ← RegisterCellType[
name: "Inverter",
ioCreator: CreateInverterIO,
expandProc: ExpandInverter,
evals: [],
ports: inverterPorts
];
[] ← RegisterCellType[
name: "Test2",
expandProc: ExpandTest2,
evals: [],
ports: NEW [PortsRep[0]]
];
END;
Setup[];
END.