<> <> <> Imports BiasTypes; Library Latch, RoseClocks; CellType "LatchTest" Expand n0, n1, n2, n3: BIT+X _ "L"; CEDAR gnd: Node _ RoseCreate.CreateNode[thisCell, "gnd", SwitchTypes.bitType, "L", SwitchTypes.refInput]; vdd: Node _ RoseCreate.CreateNode[thisCell, "vdd", SwitchTypes.bitType, "H", SwitchTypes.refInput]; biasMinus: Node _ RoseCreate.CreateNode[thisCell, "biasMinus", BiasTypes.biasType, "-"]; ; ph1, ph2: BIT; PhaseA, PhaseB: BOOL; cg: ClockGen[][]; l0: InvertingLatch[ph1, n0, n1]; l1: InvertingLatch[ph2, n1, n2]; l2: InvertingLatch[ph1, n2, n3]; l3: InvertingLatch[ph2, n3, n0]; CEDAR RoseCreate.ChangeReps[within: thisCell, a: PhaseA, b: ph1, writeA: FALSE, writeB: TRUE]; RoseCreate.ChangeReps[within: thisCell, a: PhaseB, b: ph2, writeA: FALSE, writeB: TRUE]; EndCellType