DIRECTORY
RoseTypes, RoseCreate, Asserting, BiasTypes, RoseRun, SwitchTypes, PrintTV, AMBridge, IO;

Transistors: CEDAR PROGRAM
IMPORTS RoseCreate, Asserting, BiasTypes, RoseRun, RoseTypes, SwitchTypes, PrintTV, AMBridge, IO =

BEGIN OPEN
RoseTypes, SwitchTypes, RoseRun, RoseCreate;



RegisterCells: PROC =
BEGIN
END;

Mode: PUBLIC TYPE = {Enhancement, Depletion};

Conductance: TYPE = {Off, On, Indeterminate};
ComputeState: ARRAY Mode OF ARRAY BOOL--positive-- OF ARRAY Level OF Conductance = [
Enhancement: [[On, Off, Indeterminate], [Off, On, Indeterminate]],
Depletion: [ALL[On], ALL[On]]];

Gate: TYPE = RECORD [variant: SELECT COMPUTED BOOL--biased-- FROM
FALSE => [switch: SwitchVal],
TRUE => [bh: BiasTypes.BiasHolder],
ENDCASE];

SG: TYPE = Gate[FALSE];
BG: TYPE = Gate[TRUE];

TransIORef: TYPE = REF TransIORec;
TransIORec: TYPE = MACHINE DEPENDENT RECORD [
gate(0:0..15): Gate,
ch1(1:16-bitsPerSwitchVal..15): SwitchVal,
ch2(2:16-bitsPerSwitchVal..15): SwitchVal];

BiasToLevel: ARRAY BiasTypes.Bias OF Level = [H, L];

classes: ARRAY --positive--BOOL OF ARRAY Mode OF ROPE _ [
FALSE: [Enhancement: "pE", Depletion: "pD"],
TRUE: [Enhancement: "nE", Depletion: "nD"]];


TransistorArgs: PUBLIC TYPE = RECORD [
strength: Strength _ drive,
positive: BOOL _ TRUE,
mode: Mode _ Enhancement,
unidirectional: BOOL _ FALSE,
biased: BOOL _ FALSE,
offStrength: Strength _ none];

OldTransistor: TYPE = RECORD [args: TransistorArgs, ct: CellType];
oldTransistor: LIST OF OldTransistor _ NIL;
Transistor: PUBLIC PROC [args: TransistorArgs] RETURNS [ct: CellType] =
BEGIN
FOR old: LIST OF OldTransistor _ oldTransistor, old.rest WHILE old # NIL DO
IF old.first.args = args THEN RETURN [old.first.ct]
ENDLOOP;
ct _ RoseCreate.RegisterCellType[name: TransistorName[args],
expandProc: NIL,
ioCreator: CreateTransistorIO, initializer: InitializeTransistor,
evals: [ValsChanged: TransistorValsChanged, PropQ: TransistorPropQ, InitUD: TransistorInitUD, PropUD: TransistorPropUD, FinalUD: TransistorFinalUD, EvalSimple: TransistorEvalSimple, FindVicinity: TransistorFindVicinity],
blackBox: NIL, stateToo: NIL,
ports: CreateTransistorPorts[args],
drivePrototype: NIL,
typeData: NEW [TransistorArgs _ args],
other: InitialTransistorProps[args]];
oldTransistor _ CONS[[args, ct], oldTransistor];
END;

TransistorName: PROC [args: TransistorArgs] RETURNS [name: ROPE] = {
to: IO.STREAM _ IO.ROS[]; to.PutRope["Transistor"];
TRUSTED {PrintTV.Print[tv: AMBridge.TVForReferent[NEW [TransistorArgs _ args]], put: to]};
name _ IO.RopeFromROS[to]};

CreateTransistorIO: PROC [cell: Cell] --IOCreator-- = {args: REF TransistorArgs _ NARROW[cell.type.typeData]; {OPEN args;
cell.realCellStuff.newIO _ NEW [TransIORec];
cell.realCellStuff.oldIO _ NEW [TransIORec];
cell.realCellStuff.switchIO _ NEW [TransIORec];
}};

CreateTransistorPorts: PROC [args: TransistorArgs] RETURNS [ports: Ports] =
BEGIN OPEN args;
ports _ NEW [PortsRep[3]];
ports[0] _ [0, 1, "gate", IF biased THEN BiasTypes.biasType ELSE bitType, TRUE, FALSE];
IF unidirectional
THEN {
ports[1] _ [1, 1, "ch1", bitType, TRUE, FALSE];
ports[2] _ [2, 1, "ch2", bitType, FALSE, TRUE];
}
ELSE {
ports[1] _ [1, 1, "ch1", bitType, TRUE, TRUE];
ports[2] _ [2, 1, "ch2", bitType, TRUE, TRUE];
ports[1].other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[1].other];
ports[2].other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], NARROW["ch", ROPE]], inAdditionTo: ports[2].other];
};
END;

TransistorStateRef: TYPE = REF TransistorStateRec;
TransistorStateRec: TYPE = RECORD [
conductance: Conductance
];

InitializeTransistor: Initializer = {
IF leafily THEN
BEGIN
ioRec: TransIORef _ NARROW[cell.realCellStuff.newIO];
args: REF TransistorArgs _ NARROW [cell.type.typeData];
state: TransistorStateRef _ NEW [TransistorStateRec];
cell.realCellStuff.state _ state;
BEGIN OPEN ioRec, state, args;
conductance _ ComputeState[mode][positive][WITH g: gate SELECT biased FROM FALSE => g.switch.val, TRUE => BiasToLevel[g.bh.bias], ENDCASE => ERROR];
END;
END;
};

TransistorValsChanged: CellProc =
BEGIN
sw: TransIORef _ NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
IF mode = Enhancement AND NOT biased THEN {
new: Conductance _ ComputeState[mode][positive][WITH g: gate SELECT biased FROM FALSE => g.switch.val, TRUE => BiasToLevel[g.bh.bias], ENDCASE => ERROR];
IF new # conductance THEN {
conductance _ new;
IF NOT unidirectional THEN PerturbPort[cell, 1];
PerturbPort[cell, 2];
}
};
END;
END;

TransistorPropQ: CellProc =
BEGIN
sw: TransIORef _ NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On => strength,
Off, Indeterminate => offStrength,
ENDCASE => ERROR;
IF cs > none THEN {
IF unidirectional THEN NULL ELSE
ch1.s[q] _ MAX[ch1.s[q], MIN[cs, ch2.s[q]]];
ch2.s[q] _ MAX[ch2.s[q], MIN[cs, ch1.s[q]]];
};
END;
END;

TransistorInitUD: CellProc =
BEGIN
sw: TransIORef _ NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On => strength,
Off, Indeterminate => offStrength,
ENDCASE => ERROR;
IF unidirectional AND ch1.s[q] < MIN[cs, ch2.s[q]] THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
END;
END;

TransistorPropUD: CellProc =
BEGIN
sw: TransIORef _ NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On, Indeterminate => strength,
Off => offStrength,
ENDCASE => ERROR;
IF cs > none THEN {
IF unidirectional THEN NULL
ELSE {
ch1.s[u] _ MAX[ch1.s[u], MIN[cs, ch2.s[u]]];
ch1.s[d] _ MAX[ch1.s[d], MIN[cs, ch2.s[d]]];
};
ch2.s[u] _ MAX[ch2.s[u], MIN[cs, ch1.s[u]]];
ch2.s[d] _ MAX[ch2.s[d], MIN[cs, ch1.s[d]]];
};
END;
END;

TransistorFinalUD: CellProc =
BEGIN
sw: TransIORef _ NARROW[cell.realCellStuff.switchIO];
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN sw, args, state;
cs: Strength = SELECT conductance FROM
On, Indeterminate => strength,
Off => offStrength,
ENDCASE => ERROR;
IF cs > none AND unidirectional THEN {
IF ch1.s[u] < Block[MIN[cs, ch2.s[u]], ch1.s[q]] THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
IF ch1.s[d] < Block[MIN[cs, ch2.s[d]], ch1.s[q]] THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
};
END;
END;

TransistorEvalSimple: CellProc =
BEGIN
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, args, state;
IF mode = Enhancement AND biased THEN {
new: Conductance _ ComputeState[mode][positive][WITH g: gate SELECT biased FROM FALSE => g.switch.val, TRUE => BiasToLevel[g.bh.bias], ENDCASE => ERROR];
IF new # conductance THEN {
conductance _ new;
IF NOT unidirectional THEN PerturbPort[cell, 1];
PerturbPort[cell, 2];
}
};
END;
END;

TransistorFindVicinity: PROC [cell: Cell, portIndex: CARDINAL, evenIfInput: BOOL _ FALSE] =
BEGIN
args: REF TransistorArgs _ NARROW[cell.type.typeData];
newIO: TransIORef _ NARROW[cell.realCellStuff.newIO];
state: TransistorStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN args, state;
NotOff: PROC RETURNS [no: BOOL] = INLINE {
no _ SELECT conductance FROM
On, Indeterminate => TRUE,
Off => offStrength > none,
ENDCASE => ERROR};
SELECT portIndex FROM
0 => NULL;
1 => IF NotOff[] THEN FindExteriorVicinity[cell, 3-portIndex];
2 => IF unidirectional THEN ERROR
ELSE IF NotOff[] THEN FindExteriorVicinity[cell, 3-portIndex];
ENDCASE => ERROR;
END;
END;

InitialTransistorProps: PROC [args: TransistorArgs] RETURNS [other: Assertions] = {
other _ NIL;
--designer's part: --{OPEN args;
other _ Asserting.Assert[reln: $EC, terms: LIST[NARROW["Structure", ROPE], classes[positive][mode]], inAdditionTo: other];
};
};

nE: PUBLIC CellType _ Transistor[[]];

nD: PUBLIC CellType _ Transistor[[mode:Depletion, strength:driveWeak]];

pE: PUBLIC CellType _ Transistor[[positive:FALSE]];

unE: PUBLIC CellType _ Transistor[[unidirectional:TRUE]];

unD: PUBLIC CellType _ Transistor[[mode:Depletion, strength:driveWeak, unidirectional:TRUE]];

upE: PUBLIC CellType _ Transistor[[positive:FALSE, unidirectional:TRUE]];

wpu: PUBLIC CellType _ Transistor[[strength:driveWeak, positive:FALSE, unidirectional:TRUE]];

wpd: PUBLIC CellType _ Transistor[[offStrength:driveWeak, unidirectional:TRUE, biased:TRUE]];

RegisterCells[];

END.

ΈTransistors.Mesa
created by RoseTranslate from Transistors.Rose of October 6, 1984 7:16:41 pm PDT for Spreitzer.pa at October 6, 1984 7:16:54 pm PDT
Signal Type decls
explicitly requested CEDAR:
fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
conductance _ SELECT mode FROM Enhancement => Indeterminate, Depletion => On, ENDCASE => ERROR;
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