DIRECTORY FS, IO, Rope, RoseCreate, RoseReadSim, RoseTypes, SimRead, SwitchTypes, Transistors; RoseReadSimImpl: CEDAR PROGRAM IMPORTS FS, IO, Rope, RoseCreate, SimRead, SwitchTypes, Transistors EXPORTS RoseReadSim = BEGIN ROPE: TYPE = Rope.ROPE; Cell: TYPE = RoseTypes.Cell; Node: TYPE = RoseTypes.Node; ReadSim: PUBLIC PROCEDURE [to: RoseTypes.ExpansionReceiver, within: Cell, fileName: ROPE, formatName: ROPE _ NIL--means Chipmonk .sim format--, smallNode: REAL _ 1E-14, bigNode: REAL _ 1E-12] = BEGIN EnsureNode: PROC [name: ROPE] RETURNS [node: Node]= BEGIN initialValue: ROPE _ NIL; strength: REF SwitchTypes.Strength _ SwitchTypes.refCharge; node _ RoseCreate.LookupNode[from: within, path: LIST [name]]; IF node = NIL THEN { IF name.Equal["VDD", FALSE] THEN {initialValue _ "H"; strength _ SwitchTypes.refInput} ELSE IF name.Equal["GND", FALSE] THEN {initialValue _ "L"; strength _ SwitchTypes.refInput}; node _ to.class.NodeInstance[ erInstance: to.instance, name: name, type: SwitchTypes.bitType, initialValue: initialValue, initData: strength]; }; END; GotTransistor: PROCEDURE [pd: SimRead.ParseData, cd: SimRead.ClientData] = BEGIN gate: Node _ EnsureNode[pd.gate]; [] _ EnsureNode[pd.source]; [] _ EnsureNode[pd.drain]; [] _ to.class.CellInstance[ erInstance: to.instance, instanceName: IO.PutFR["t%g", IO.card[tCount _ tCount + 1]], typeName: Transistors.Transistor[[ strength: SELECT pd.transistorType FROM nD, pD => driveWeak, nE, pE => drive, ENDCASE => ERROR, positive: SELECT pd.transistorType FROM nE, nD => TRUE, pE, pD => FALSE, ENDCASE => ERROR, mode: SELECT pd.transistorType FROM nD, pD => Depletion, nE, pE => Enhancement, ENDCASE => ERROR]].name, interfaceNodes: IO.PutFR["gate: %g, ch1: %g, ch2: %g", IO.rope[pd.gate], IO.rope[pd.source], IO.rope[pd.drain]] ]; AddCap[gate, pd]; END; tCount: INT _ 0; GotNode: PROCEDURE [pd: SimRead.ParseData, cd: SimRead.ClientData] = {AddCap[EnsureNode[pd.name], pd]}; AddCap: PROC [node: Node, pd: SimRead.ParseData] = BEGIN cap: REAL; size: SwitchTypes.Strength; IF pd.capEstimateClass = ignore OR node.name.Equal["vdd", FALSE] OR node.name.Equal["gnd", FALSE] THEN RETURN; cap _ SwitchTypes.GetCapacitance[node]; IF (pd.capEstimateClass = absolute) AND (cap > 0) THEN ERROR; cap _ cap + pd.capacitanceEstimate; size _ IF cap < smallNode THEN chargeWeak ELSE IF cap > bigNode THEN chargeStrong ELSE charge; SwitchTypes.SetCapacitance[node, cap]; SwitchTypes.SetSizes[node, size, size]; END; from: IO.STREAM _ NIL; roseSimClient: SimRead.Client; format: SimRead.Format _ SimRead.GetFormat[IF formatName # NIL THEN formatName ELSE "Chipmonk"]; TRUSTED {roseSimClient _ NEW [SimRead.ClientRep _ [ GotTransistor: GotTransistor, GotNode: GotNode]]}; from _ FS.StreamOpen[fileName: fileName]; SimRead.FromStream[from: from, client: roseSimClient, format: format]; from.Close[]; END; END. |[Indigo]2.6>Rosemary.DF=>RoseReadSimImpl.Mesa Last Edited by: Spreitzer, September 15, 1984 8:02:19 pm PDT ‌ت·– "cedar" styleکJ™7J™ڑ‌œ‌œ‌œکڑ‌œ‌œکKڑ‌œ6ک:—ڑ‌œ‌œ‌œک Kڑ‌œ7ک;—ڑœکKڑœکKکKڑœکKڑœکKڑœک—Kک—Kڑ‌œک—ڑں œ‌ œ2کJKڑ‌کKک!KکKکڑœکKڑœکKڑœ‌œ‌œک<ک"ڑœ ‌œ‌ک'KڑœکKڑœکKڑ‌œ‌œک—ڑœ ‌œ‌ک'Kڑœ ‌œکKڑœ ‌œکKڑ‌œ‌œک—ڑœ‌œ‌ک#KڑœکKڑœکKڑ‌œ‌œک——ڑœ‌œ$ک6Kڑ‌œ‌œ‌œک8—Kڑœک—KکKڑ‌œک—Kڑœ‌œکڑںœ‌ œ2کDKڑœ"ک"—ڑںœ‌œ&ک2Kڑ‌کKڑœ‌ک KڑœکKڑ‌œ‌œ‌œ‌œ‌œ‌œ‌œکnKڑœ'ک'Kڑ‌œ"‌œ‌œ‌œک=Kڑœ#ک#Kڑ œ‌œ‌œ‌œ‌œ‌œ‌œک^Kک&Kڑœ'ک'Kڑ‌œک—Kڑœ‌œ‌œ‌œکKڑœکKڑ œ+‌œ‌œ‌œ‌œ ک`ڑ‌œ‌œک3KڑœکKڑœک—Kڑœ)ک)KکFKک Kڑ‌œک—KکKڑ‌œک—…—([