<> <> <> Library Transistors; Imports BitSwOps; CELLTYPE "Inverter" PORTS [inBIT+S+X] EvalSimple out _ BitSwOps.IBISS[in.val#H, out, u, [driveWeak, driveWeak]]; out _ BitSwOps.IBISS[in.val#L, out, d, [none, drive]]; ENDCELLTYPE; CELLTYPE "SpecialTest" PORTS [in1, in2, connect< BIT+X] Expand o1, o2: BIT+X; I1: Inverter[in: in1, out: o1]; I2: Inverter[in: in2, out: o2]; P: nE[gate: connect, ch1: o1, ch2: o2] ENDCELLTYPE