Shifting.Rose
last edited by Barth, March 7, 1983 12:19 pm
Last Edited by: Spreitzer, October 2, 1984 11:07:35 am PDT
Imports IO, Mnemonics, RoseRun, RoseTypes, RoseClocks, SRHC;
Library RoseClocks, SRHC;
SRWC:
LAMBDA [s1, s2: |[0 .. 16)|]
RETURN
CELLTYPE AutoName
PORTS [phi1, phi2<, input<INT[4], output>INT[4]]
Assert ((EC "Structure" "SRWC") (Zwop 42))
Expand
middle: INT[4];
First: SRHC[s1][input:input, clock:phi1, output:middle];
second: SRHC[s2][input:middle, clock:phi2--, output: output--]
ENDCELLTYPE;
NBitSR:
LAMBDA [n: |
CARDINAL|]
RETURN
CELLTYPE AutoName
PORTS [phi1, phi2<, input<INT[4]-(XPhobic)-(Foo bar), output>INT[4]]
Expand
CEDAR
prev, next: ROPE;
next ← "input";
FOR i:
CARDINAL
IN [0..n)
DO
prev ← next;
IF n # i+1
THEN
BEGIN
next ← IO.PutFR["node%g", IO.card[i+1]];
[] ← to.class.NodeInstance[erInstance: to.instance, name: next, type: NumTypes.NumType[4]];
END
ELSE next ← "output";
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["SRWC%g", IO.card[i]], typeName: SRWC[[13, 7]].name, interfaceNodes: IO.PutFR["input: %g, phi2: phi2, output: %g", IO.rope[prev], IO.rope[next]]];
ENDLOOP;
BlackBoxTest
phi1 ← TRUE;
phi2 ← TRUE;
FOR i: [0 .. 16)
IN [0 .. 16)
DO
input ← i;
[] ← RoseRun.Eval[handle];
IF output # i THEN SIGNAL Stop[IO.PutFR["Got %g from %g", IO.card[output], IO.card[input]]];
ENDLOOP;
ENDCELLTYPE;
CELLTYPE "Fooey" ENDCELLTYPE;
CELLTYPE "
Counter"
PORTS [phi1, phi2<, count>INT[4], report=Mnemonic["ShiftCounterOps"]]
InittableState
next: [0..16) ← 5
EvalSimple
IF phi1 THEN next ← (count + 1) MOD 16;
IF phi2 THEN count ← next;
report ← reports[phi1][phi2];
ENDCELLTYPE;
CEDAR
reports:
ARRAY
BOOLEAN
OF
ARRAY
BOOLEAN
OF ShiftCounterOps ←
[[BothOff, Storing], [Looking, BothOn]];
;
TopNBitSR:
LAMBDA [n: |
CARDINAL|]
RETURN
CELLTYPE AutoName
PORTS []
Expand
front, back: INT[4];
PhaseA, clk2: BOOL ← "FALSE";
sink: Mnemonic["ShiftCounterOps"];
clkGen: ClockGen[][PhaseA: PhaseA, PhaseB: clk2];
cntr: Counter[phi1: PhaseA, phi2: clk2, count: front, report: sink];
shifter: NBitSR[n][input: front, output: back, phi1: PhaseA, phi2: clk2]
ENDCELLTYPE