RoseTest3.Rose
Last Edited by: Spreitzer, June 26, 1984 3:23:19 pm PDT
Library RoseClocks;
CELLTYPE
CardCounter
PORTS [PhaseA, PhaseB<BOOL, count>INT[16]]
InittableState
next: CARDINAL ← 7
EvalSimple
IF PhaseA THEN next ← next + 1;
IF PhaseB THEN count ← next;
ENDCELLTYPE;
Modulator:
LAMBDA [modulus: |
INTEGER|]
RETURN
CELLTYPE AutoName
PORTS [count< INT[16], ans>INT[16]]
EvalSimple
IF (count MOD modulus) = 0 THEN ans ← count
ENDCELLTYPE;
CELLTYPE
RoseTest3
Expand
PhaseA, PhaseB: BOOL;
count, ans: INT[16];
clkGen: ClockGen[];
counter: CardCounter[];
mod3: Modulator[3][];
mod5: Modulator[3][]
ENDCELLTYPE