CellType "
Inverter"
Ports [in<BIT-(XPhillic), out=BIT-(XPhillic), gnd, vdd<BIT]
Expand
pd: unE[in, gnd, out];
pu: unD[out, vdd, out]
EndCellType;
CellType "
Test2B"
Ports [in1, in2, sel1, sel2<BIT-(XPhillic), ans>BIT-(XPhillic), gnd, vdd<BIT]
BlackBoxTest
gnd ← [s: [input, none, input], val: L];
vdd ← [s: [input, input, none], val: H];
ans ← [s: [none, none, none], val: X];
FOR in1L: Level
IN Level
DO
FOR in2L: Level
IN Level
DO
IF in2L < in1L THEN LOOP;
FOR sel1L: Level
IN Level
DO
FOR sel2L: Level
IN Level
DO
IF in2L = in1L AND sel2L < sel1L THEN LOOP;
in1 ← FromLevel[in1L];
in2 ← FromLevel[in2L];
sel1 ← FromLevel[sel1L];
sel2 ← FromLevel[sel2L];
[] ← RoseRun.Eval[handle: handle];
ENDLOOP;
ENDLOOP;
ENDLOOP;
ENDLOOP;
Expand
out1, out2: BIT-(XPhillic);
inv1: Inverter[in1, out1];
inv2: Inverter[in2, out2];
pass1: nE[sel1, out1, ans];
pass2: nE[sel2, out2, ans]
EndCellType;