DIRECTORY RoseCreate, RoseTypes, SwitchTypes; RoseTest: CEDAR PROGRAM IMPORTS RoseCreate, SwitchTypes = BEGIN OPEN SwitchTypes, RoseCreate, RoseTypes; ExpandTest1: ExpandProc--PROC [thisCell: Cell, initData: REF ANY]-- = BEGIN vdd: Node _ CreateNode[thisCell, "vdd", bitType, "H", refInput]; gnd: Node _ CreateNode[thisCell, "gnd", bitType, "L", refInput]; in: Node _ CreateNode[thisCell, "in", bitType]; out: Node _ CreateNode[thisCell, "out", bitType]; pd: Cell _ CreateCell[thisCell, "pd", "NETrans", "in, gnd, out"]; pu: Cell _ CreateCell[thisCell, "pu", "NDTrans", "out, vdd, out", refDriveWeak]; END; InterterIORef: TYPE = REF InverterIORec; InverterIORec: TYPE = MACHINE DEPENDENT RECORD [ vdd(0:16-bitsPerSwitchVal..15): SwitchVal, gnd(1:16-bitsPerSwitchVal..15): SwitchVal, in(2:16-bitsPerSwitchVal..15): SwitchVal, out(3:16-bitsPerSwitchVal..15): SwitchVal]; inverterPorts: Ports _ NEW [PortsRep[4]]; CreateInverterIO: IOCreator--PROC [cell: Cell, initData: REF ANY]-- = BEGIN cell.realCellStuff.newIO _ NEW [InverterIORec]; cell.realCellStuff.oldIO _ NEW [InverterIORec]; END; ExpandInverter: ExpandProc--PROC [thisCell: Cell, initData: REF ANY]-- = BEGIN pd: Cell _ CreateCell[thisCell, "pd", "PassTrans", "in, gnd, out"]; pu: Cell _ CreateCell[thisCell, "pu", "PullupTrans", "out, vdd, out"]; END; ExpandTest2: ExpandProc--PROC [thisCell: Cell, initData: REF ANY]-- = BEGIN vdd: Node _ CreateNode[thisCell, "vdd", bitType, "H", refInput]; gnd: Node _ CreateNode[thisCell, "gnd", bitType, "L", refInput]; in1: Node _ CreateNode[thisCell, "in1", bitType, NIL, refInput]; in2: Node _ CreateNode[thisCell, "in2", bitType, NIL, refInput]; out1: Node _ CreateNode[thisCell, "out1", bitType]; out2: Node _ CreateNode[thisCell, "out2", bitType]; sel1: Node _ CreateNode[thisCell, "sel1", bitType, NIL, refInput]; sel2: Node _ CreateNode[thisCell, "sel2", bitType, NIL, refInput]; ans: Node _ CreateNode[thisCell, "ans", bitType]; inv1: Cell _ CreateCell[thisCell, "inv1", "Inverter", "in: in1, out: out1"]; inv2: Cell _ CreateCell[thisCell, "inv2", "Inverter", "in: in2, out: out2"]; pass1: Cell _ CreateCell[thisCell, "pass1", "NETrans", "sel1, out1, ans"]; pass2: Cell _ CreateCell[thisCell, "pass2", "NETrans", "sel2, out2, ans"]; END; Setup: PROC = BEGIN [] _ RegisterCellClass[ className: "Test1", expandProc: ExpandTest1, evals: [], ports: NEW [PortsRep[0]] ]; inverterPorts[0] _ [0, 1, "vdd", bitType, TRUE, FALSE]; inverterPorts[1] _ [1, 1, "gnd", bitType, TRUE, FALSE]; inverterPorts[2] _ [2, 1, "in", bitType, TRUE, FALSE]; inverterPorts[3] _ [3, 1, "out", bitType, TRUE, TRUE]; [] _ RegisterCellClass[ className: "Inverter", ioCreator: CreateInverterIO, expandProc: ExpandInverter, evals: [], ports: inverterPorts ]; [] _ RegisterCellClass[ className: "Test2", expandProc: ExpandTest2, evals: [], ports: NEW [PortsRep[0]] ]; END; Setup[]; END. hRoseTest.Mesa Last Edited by: Spreitzer, May 28, 1984 11:40:00 am PDT fill0(0:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), fill3(3:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]), Κo– "cedar" style˜J™ J™7J˜IcodešΟk œ$˜-K˜šΠbxœœ˜Kšœ˜!—K˜Kšœœ$˜.K˜šΟn œ Οc,œ˜EKš˜K˜@K˜@K˜/K˜1KšœA˜AKšœP˜PKšœ˜—K˜Kšœœœ˜(š œœœ œœ˜0K™FK˜*K™FK˜*K™FK˜)K™FK˜+—K˜Kšœœ˜)K˜šŸœ  (œ˜EKš˜Kšœœ˜/Kšœœ˜/Kšœ˜—K˜šŸœ  ,œ˜HKš˜KšœC˜CKšœF˜FKšœ˜—K˜šŸ œ  ,œ˜EKš˜K˜@K˜@K˜@K˜@K˜3K˜3K˜BK˜BK˜1K˜LK˜LK˜JK˜JKšœ˜—K˜šŸœœ˜ Kš˜˜K˜K˜K˜ Kšœœ˜K˜—K˜Kšœ*œœ˜7Kšœ*œœ˜7Kšœ)œœ˜6Kšœ*œœ˜6˜K˜K˜K˜K˜ Kšœ˜K˜—K˜˜K˜K˜K˜ Kšœœ˜K˜—Kšœ˜—K˜K˜K˜Kšœ˜—…— <