[Indigo]<Rosemary>2.4>Rosemary.DF=>TransistorsImpl.Mesa
Last Edited by: Spreitzer, May 28, 1984 11:40:27 am PDT
DIRECTORY RoseCreate, RoseRun, RoseTypes, SwitchTypes;
TransistorsImpl:
CEDAR
PROGRAM
IMPORTS RoseCreate, RoseRun, RoseTypes, SwitchTypes =
BEGIN OPEN SwitchTypes, RoseRun, RoseCreate, RoseTypes;
NState: ARRAY Level OF Level = [L, X, H];
PState: ARRAY Level OF Level = [H, X, L];
TransIORef: TYPE = REF TransIORec;
TransIORec:
TYPE =
MACHINE
DEPENDENT
RECORD [
fill0(0:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
gate(0:16-bitsPerSwitchVal..15): SwitchVal,
fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
ch1(1:16-bitsPerSwitchVal..15): SwitchVal,
fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
ch2(2:16-bitsPerSwitchVal..15): SwitchVal];
TransStateRef: TYPE = REF TransStateRec;
TransStateRec:
TYPE =
RECORD [
strength: Strength,
conductance: Level];
transPorts: Ports ← NEW [PortsRep[3]];
directionalTransPorts: Ports ← NEW [PortsRep[3]];
TransIOCreator: IOCreator
--PROC [cell: Cell, initData: REF ANY]-- =
BEGIN
cell.realCellStuff.oldIO ← NEW [TransIORec];
cell.realCellStuff.newIO ← NEW [TransIORec];
cell.realCellStuff.switchIO ← NEW [TransIORec];
END;
ETransInitializer: Initializer
--PROCEDURE [cell: Cell, initData: REF ANY, leafily: BOOLEAN]-- =
BEGIN
IF leafily
THEN
BEGIN
rs: REF Strength ← NARROW[initData];
cell.realCellStuff.state ← NEW [TransStateRec ← [IF rs = NIL THEN drive ELSE rs^, X]];
END;
END;
DTransInitializer: Initializer
--PROCEDURE [cell: Cell, initData: REF ANY, leafily: BOOLEAN]-- =
BEGIN
IF leafily
THEN
BEGIN
rs: REF Strength ← NARROW[initData];
cell.realCellStuff.state ← NEW [TransStateRec ← [IF rs = NIL THEN drive ELSE rs^, H]];
END;
END;
PullupTransInitializer: Initializer
--PROCEDURE [cell: Cell, initData: REF ANY, leafily: BOOLEAN]-- =
BEGIN
IF leafily
THEN
BEGIN
rs: REF Strength ← NARROW[initData];
cell.realCellStuff.state ← NEW [TransStateRec ← [IF rs = NIL THEN driveWeak ELSE rs^, H]];
END;
END;
NETransValsChanged: CellProc
--PROC [cell: Cell]-- =
BEGIN
io: TransIORef ← NARROW[cell.realCellStuff.switchIO];
state: TransStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN OPEN state, io;
IF NState[gate.val] # conductance
THEN
{conductance ← NState[gate.val]; PerturbPort[cell, 1]; PerturbPort[cell, 2]};
END;
END;
PETransValsChanged: CellProc
--PROC [cell: Cell]-- =
BEGIN
io: TransIORef ← NARROW[cell.realCellStuff.switchIO];
state: TransStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN OPEN state, io;
IF PState[gate.val] # conductance
THEN
{conductance ← PState[gate.val]; PerturbPort[cell, 1]; PerturbPort[cell, 2]};
END;
END;
TransFindVicinity:
PROC [cell: Cell, index:
CARDINAL] =
BEGIN
state: TransStateRef ← NARROW[cell.realCellStuff.state];
SELECT index
FROM
0 => NULL;
1, 2 => IF state.conductance # L THEN FindExteriorVicinity[cell, 3-index];
ENDCASE => ERROR;
END;
DirTransFindVicinity:
PROC [cell: Cell, index:
CARDINAL] =
BEGIN
state: TransStateRef ← NARROW[cell.realCellStuff.state];
SELECT index
FROM
0 => NULL;
1 => IF state.conductance # L THEN FindExteriorVicinity[cell, 3-index];
2 => ERROR;
ENDCASE => ERROR;
END;
TransPropQ: CellProc
--PROC [cell: Cell]-- =
BEGIN
io: TransIORef ← NARROW[cell.realCellStuff.switchIO];
state: TransStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN OPEN state, io;
IF conductance =
H
THEN {
ch1.s[q] ← MAX[ch1.s[q], MIN[strength, ch2.s[q]]];
ch2.s[q] ← MAX[ch2.s[q], MIN[strength, ch1.s[q]]];
};
END;
END;
DirTransPropQ: CellProc
--PROC [cell: Cell]-- =
BEGIN
io: TransIORef ← NARROW[cell.realCellStuff.switchIO];
state: TransStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN OPEN state, io;
IF conductance =
H
THEN {
IF ch1.s[q] <
MIN[strength, ch2.s[q]]
THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
ch2.s[q] ← MAX[ch2.s[q], MIN[strength, ch1.s[q]]];
};
END;
END;
TransPropUD: CellProc
--PROC [cell: Cell]-- =
BEGIN
io: TransIORef ← NARROW[cell.realCellStuff.switchIO];
state: TransStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN OPEN state, io;
IF conductance #
L
THEN
BEGIN
ch1.s[u] ← MAX[ch1.s[u], MIN[strength, ch2.s[u]]];
ch2.s[u] ← MAX[ch2.s[u], MIN[strength, ch1.s[u]]];
ch1.s[d] ← MAX[ch1.s[d], MIN[strength, ch2.s[d]]];
ch2.s[d] ← MAX[ch2.s[d], MIN[strength, ch1.s[d]]];
END;
END;
END;
DirTransPropUD: CellProc
--PROC [cell: Cell]-- =
BEGIN
io: TransIORef ← NARROW[cell.realCellStuff.switchIO];
state: TransStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN OPEN state, io;
IF conductance #
L
THEN
BEGIN
IF ch1.s[u] < Block[
MIN[strength, ch2.s[u]], ch1.s[q]]
THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
ch2.s[u] ← MAX[ch2.s[u], MIN[strength, ch1.s[u]]];
IF ch1.s[d] < Block[
MIN[strength, ch2.s[d]], ch1.s[q]]
THEN
ERROR Error["Backward flow across unidirectional transistor!", cell];
ch2.s[d] ← MAX[ch2.s[d], MIN[strength, ch1.s[d]]];
END;
END;
END;
Setup:
PROC =
BEGIN
transPorts[0] ← [0, 1, "gate", bitType, TRUE, FALSE];
transPorts[1] ← [1, 1, "ch1", bitType, TRUE, TRUE];
transPorts[2] ← [2, 1, "ch2", bitType, TRUE, TRUE];
directionalTransPorts[0] ← [0, 1, "gate", bitType, TRUE, FALSE];
directionalTransPorts[1] ← [1, 1, "in", bitType, TRUE, FALSE];
directionalTransPorts[2] ← [2, 1, "out", bitType, FALSE, TRUE];
[] ← RegisterCellClass[
className: "NETrans",
ioCreator: TransIOCreator,
initializer: ETransInitializer,
evals: [ValsChanged: NETransValsChanged,
FindVicinity: TransFindVicinity,
PropQ: TransPropQ,
PropUD: TransPropUD],
ports: transPorts];
[] ← RegisterCellClass[
className: "PETrans",
ioCreator: TransIOCreator,
initializer: ETransInitializer,
evals: [ValsChanged: PETransValsChanged,
FindVicinity: TransFindVicinity,
PropQ: TransPropQ,
PropUD: TransPropUD],
ports: transPorts];
[] ← RegisterCellClass[
className: "PDTrans",
ioCreator: TransIOCreator,
initializer: DTransInitializer,
evals: [
FindVicinity: TransFindVicinity,
PropQ: TransPropQ,
PropUD: TransPropUD],
ports: transPorts];
[] ← RegisterCellClass[
className: "NDTrans",
ioCreator: TransIOCreator,
initializer: DTransInitializer,
evals: [
FindVicinity: TransFindVicinity,
PropQ: TransPropQ,
PropUD: TransPropUD],
ports: transPorts];
[] ← RegisterCellClass[
className: "PassTrans",
ioCreator: TransIOCreator,
initializer: ETransInitializer,
evals: [ValsChanged: NETransValsChanged,
FindVicinity: DirTransFindVicinity,
PropQ: DirTransPropQ,
PropUD: DirTransPropUD],
ports: directionalTransPorts];
[] ← RegisterCellClass[
className: "PullupTrans",
ioCreator: TransIOCreator,
initializer: PullupTransInitializer,
evals: [
FindVicinity: DirTransFindVicinity,
PropQ: DirTransPropQ,
PropUD: DirTransPropUD],
ports: directionalTransPorts];
END;
Setup[];
END.