Shifting.Rose
last edited by Barth, March 7, 1983 12:19 pm
Last Edited by: Spreitzer, March 4, 1984 1:27:32 pm PST
Imports IO, Mnemonics, RoseRun, RoseTypes;
Library RoseClocks, SRHC;
SRWC: CELL [phi1, phi2<, input<INT[4], output>INT[4]]
Expand
middle: INT[4];
First: SRHC[input:input, clock:phi1, output:middle] init NEW [SRHC.SRHCInitRec ← [3]]|;
second: SRHC[input:middle, clock:phi2--, output: output--]
ENDCELL;
NBitSR: CELL [phi1, phi2<, input<INT[4], output>INT[4]]
InitData
n: CARDINAL
Expand
CEDAR
prev, next: ROPE;
next ← "input";
FOR i: CARDINAL IN [0..n) DO
prev ← next;
IF n # i+1 THEN
BEGIN
next ← IO.PutFR["node%g", IO.card[i+1]];
[] ← RoseCreate.CreateNode[within: thisCell, name: next, type: NumTypes.NumType[4]];
END
ELSE next ← "output";
[] ← RoseCreate.CreateCell[within: thisCell, instanceName: IO.PutFR["SRWC%g", IO.card[i]], className: "SRWC", interfaceNodes: IO.PutFR["input: %g, phi2: phi2, output: %g", IO.rope[prev], IO.rope[next]]];
ENDLOOP;
BlackBoxTest
phi1 ← TRUE;
phi2 ← TRUE;
FOR i: [0 .. 16) IN [0 .. 16) DO
input ← i;
[] ← RoseRun.Eval[handle];
IF output # i THEN SIGNAL Stop[IO.PutFR["Got %g from %g", IO.card[output], IO.card[input]]];
ENDLOOP;
ENDCELL;
Fooey: CELL [] ENDCELL;
CEDAR
InitFor: PROC [n: CARDINAL] RETURNS [NBitSRInitRef] =
{RETURN [NEW [NBitSRInitRec ← [n]]]};
;
Counter: CELL [phi1, phi2<, count>INT[4], report=Mnemonic["ShiftCounterOps"]]
State
next: [0..16) ← 5
EvalSimple
IF phi1 THEN next ← (count + 1) MOD 16;
IF phi2 THEN count ← next;
report ← reports[phi1][phi2];
ENDCELL;
CEDAR
reports: ARRAY BOOLEAN OF ARRAY BOOLEAN OF ShiftCounterOps ←
[[BothOff, Storing], [Looking, BothOn]];
;
TopNBitSR: CELL NULL
Expand
front, back: INT[4];
PhaseA, clk2: BOOL ← "FALSE";
sink: Mnemonic["ShiftCounterOps"];
clkGen: ClockGen[PhaseA: PhaseA, PhaseB: clk2];
cntr: Counter[phi1: PhaseA, phi2: clk2, count: front, report: sink];
shifter: NBitSR[input: front, output: back, phi1: PhaseA, phi2: clk2] init initData|
ENDCELL