<> <> Library RoseClocks; CardCounter: CELL [PhaseA, PhaseBINT[16]] InittableState next: CARDINAL _ 7 EvalSimple IF PhaseA THEN next _ next + 1; IF PhaseB THEN count _ next; ENDCELL; Modulator: CELL [count< INT[16], ans>INT[16]] State modulus: CARDINAL Initializer modulus _ NARROW[initData, REF INTEGER]^ EvalSimple IF (count MOD modulus) = 0 THEN ans _ count ENDCELL; RoseTest3: CELL [] Expand PhaseA, PhaseB: BOOL; count, ans: INT[16]; clkGen: ClockGen[]; counter: CardCounter[]; mod3: Modulator[] init NEW [INTEGER _ 3]|; mod5: Modulator[] init NEW [INTEGER _ 5]| ENDCELL