RoseTest3.Rose
Last Edited by: Spreitzer, May 28, 1984 12:14:05 pm PDT
Library RoseClocks;
CardCounter:
CELL [PhaseA, PhaseB<
BOOL, count>
INT[16]]
InittableState
next:
CARDINAL ← 7
EvalSimple
IF PhaseA
THEN next ← next + 1;
IF PhaseB
THEN count ← next;
ENDCELL;
Modulator:
CELL [count<
INT[16], ans>
INT[16]]
State
modulus:
CARDINAL
Initializer
modulus ←
NARROW[initData,
REF
INTEGER]^
EvalSimple
IF (count
MOD modulus) = 0
THEN ans ← count
ENDCELL;
RoseTest3:
CELL []
Expand
PhaseA, PhaseB:
BOOL;
count, ans:
INT[16];
clkGen: ClockGen[];
counter: CardCounter[];
mod3: Modulator[] init
NEW [
INTEGER ← 3]|;
mod5: Modulator[] init
NEW [
INTEGER ← 5]|
ENDCELL