RoseTest.Mesa
Last Edited by: Spreitzer, May 28, 1984 11:40:00 am PDT
DIRECTORY RoseCreate, RoseTypes, SwitchTypes;
RoseTest:
CEDAR
PROGRAM
IMPORTS RoseCreate, SwitchTypes =
BEGIN OPEN SwitchTypes, RoseCreate, RoseTypes;
ExpandTest1: ExpandProc
--PROC [thisCell: Cell, initData: REF ANY]-- =
BEGIN
vdd: Node ← CreateNode[thisCell, "vdd", bitType, "H", refInput];
gnd: Node ← CreateNode[thisCell, "gnd", bitType, "L", refInput];
in: Node ← CreateNode[thisCell, "in", bitType];
out: Node ← CreateNode[thisCell, "out", bitType];
pd: Cell ← CreateCell[thisCell, "pd", "NETrans", "in, gnd, out"];
pu: Cell ← CreateCell[thisCell, "pu", "NDTrans", "out, vdd, out", refDriveWeak];
END;
InterterIORef: TYPE = REF InverterIORec;
InverterIORec:
TYPE =
MACHINE
DEPENDENT
RECORD [
fill0(0:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
vdd(0:16-bitsPerSwitchVal..15): SwitchVal,
fill1(1:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
gnd(1:16-bitsPerSwitchVal..15): SwitchVal,
fill2(2:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
in(2:16-bitsPerSwitchVal..15): SwitchVal,
fill3(3:0..15-bitsPerSwitchVal): [0 .. TwoToThe[16-bitsPerSwitchVal]),
out(3:16-bitsPerSwitchVal..15): SwitchVal];
inverterPorts: Ports ← NEW [PortsRep[4]];
CreateInverterIO: IOCreator
--PROC [cell: Cell, initData: REF ANY]-- =
BEGIN
cell.realCellStuff.newIO ← NEW [InverterIORec];
cell.realCellStuff.oldIO ← NEW [InverterIORec];
END;
ExpandInverter: ExpandProc
--PROC [thisCell: Cell, initData: REF ANY]-- =
BEGIN
pd: Cell ← CreateCell[thisCell, "pd", "PassTrans", "in, gnd, out"];
pu: Cell ← CreateCell[thisCell, "pu", "PullupTrans", "out, vdd, out"];
END;
ExpandTest2: ExpandProc
--PROC [thisCell: Cell, initData: REF ANY]-- =
BEGIN
vdd: Node ← CreateNode[thisCell, "vdd", bitType, "H", refInput];
gnd: Node ← CreateNode[thisCell, "gnd", bitType, "L", refInput];
in1: Node ← CreateNode[thisCell, "in1", bitType, NIL, refInput];
in2: Node ← CreateNode[thisCell, "in2", bitType, NIL, refInput];
out1: Node ← CreateNode[thisCell, "out1", bitType];
out2: Node ← CreateNode[thisCell, "out2", bitType];
sel1: Node ← CreateNode[thisCell, "sel1", bitType, NIL, refInput];
sel2: Node ← CreateNode[thisCell, "sel2", bitType, NIL, refInput];
ans: Node ← CreateNode[thisCell, "ans", bitType];
inv1: Cell ← CreateCell[thisCell, "inv1", "Inverter", "in: in1, out: out1"];
inv2: Cell ← CreateCell[thisCell, "inv2", "Inverter", "in: in2, out: out2"];
pass1: Cell ← CreateCell[thisCell, "pass1", "NETrans", "sel1, out1, ans"];
pass2: Cell ← CreateCell[thisCell, "pass2", "NETrans", "sel2, out2, ans"];
END;
Setup:
PROC =
BEGIN
[] ← RegisterCellClass[
className: "Test1",
expandProc: ExpandTest1,
evals: [],
ports: NEW [PortsRep[0]]
];
inverterPorts[0] ← [0, 1, "vdd", bitType, TRUE, FALSE];
inverterPorts[1] ← [1, 1, "gnd", bitType, TRUE, FALSE];
inverterPorts[2] ← [2, 1, "in", bitType, TRUE, FALSE];
inverterPorts[3] ← [3, 1, "out", bitType, TRUE, TRUE];
[] ← RegisterCellClass[
className: "Inverter",
ioCreator: CreateInverterIO,
expandProc: ExpandInverter,
evals: [],
ports: inverterPorts
];
[] ← RegisterCellClass[
className: "Test2",
expandProc: ExpandTest2,
evals: [],
ports: NEW [PortsRep[0]]
];
END;
Setup[];
END.