[Indigo]<Rosemary>2.5>RoseCreate.Mesa!1

[Indigo]<Rosemary>2.3>Rosemary.df=>RoseCreate.Mesa

Last Edited by: Spreitzer, May 1, 1984 4:09:34 pm PDT

DIRECTORY RoseTypes;

RoseCreate: CEDAR DEFINITIONS =

BEGIN OPEN RoseTypes;

InterfaceMismatch: ERROR [cell: Cell,

index: CARDINAL,

expected, got: NodeType];

RegisterCellClass: PROC [className: ROPE, expandProc: ExpandProc ← NIL, ioCreator: IOCreator ← NIL, initializer: Initializer ← NIL, evals: EvalProcs, blackBox, stateToo: CellTestProc ← NIL, ports: Ports, drivePrototype: REF ANY ← NIL, classData: REF ANY ← NIL] RETURNS [class: CellClass];

GetCellClass: PROC [className: ROPE] RETURNS [class: CellClass];

CreateSim: PROC [steady: BOOL] RETURNS [sim: Simulation];

CreateTopCell: PROC [instanceName, className: ROPE, decider: ExpandDeciderClosure, initData: REF ANY ← NIL, steady: BOOL ← TRUE] RETURNS [cell: Cell, osim: Simulation];

interfaceNodes must be empty at the top.

steady indicates whether this is for working on the steady-state, or initialization.

ExpandDeciderClosure: TYPE = REF ExpandDeciderClosureRep;

ExpandDeciderClosureRep: TYPE = RECORD [

Decide: ExpandDecider, otherData: REF ANY];

ExpandDecider: TYPE = PROC [cell: Cell, otherData: REF ANY] RETURNS [ExpandDecision];

Possible: PROC [cell: Cell, whatToDo: ExpandDecision] RETURNS [possible: BOOLEAN];

CreateTest: PROC [rootName, testerName, testeeName, className: ROPE, stateToo: BOOL ← TRUE, decider: ExpandDeciderClosure, initData: REF ANY ← NIL, steady: BOOL ← TRUE] RETURNS [root: Cell, osim: Simulation, cth: CellTestHandle];

WrapTop: PROC [rootName, className: ROPE, decider: ExpandDeciderClosure, initData: REF ANY ← NIL, clocks: ROPE ← NIL, steady: BOOL ← TRUE] RETURNS [root: Cell, osim: Simulation];

Given a class with a non-empty interface, this will create (if necessary) and instantiate a class, with an empty interface, whose ExpandProc instantiates the given class, and the nodes it needs. The instance name used for the component is the class name with its first character lowercased. If clocks # NIL, a clock generator will also be instantiated, with its outputs connected to the nodes named in clocks.

CreateCell: PROC [within: Cell, instanceName, className, interfaceNodes: ROPE, initData: REF ANY ← NIL] RETURNS [cell: Cell];

CreateNode: PROC [within: Cell, name: ROPE, type: NodeType, initialValue: ROPE ← NIL, initData: REF ANY ← NIL] RETURNS [node: Node];

PortsFromROPE: PROC [asRope: ROPE] RETURNS [ports: Ports];

PortsFromFile: PROC [fileName: ROPE] RETURNS [ports: Ports];

PortsFromStream: PROC [stream: STREAM] RETURNS [ports: Ports];

SplitJoin: PROC [within: Cell, a, b: StretchList, writeA, writeB: BOOLEAN];

This proc declares the alignment of two lists of subarrays or elements.

ChangeReps: PROC [within: Cell, a, b: Node, writeA, writeB: BOOLEAN];

This proc declares that the two nodes are electrically identical, but use different representations during simulation.

DecideFromFile: PROC [fileName: ROPE] RETURNS [dff: ExpandDeciderClosure];

LookupCell: PROC [

path: RopeList,

from: Cell ← NIL --NIL means first name names root--]

RETURNS [cell: Cell];

LookupNode: PROC [

path: RopeList,

from: Cell ← NIL]

RETURNS [node: Node];

EnsureEnvironment: PROC [in: Cell, forClass: CellClass];

MirrorPorts: PROC [fwd: Ports, alwaysOutput, alwaysInput: BOOL ← FALSE] RETURNS [bkwd: Ports];

MakeMirrorIO: PROC [cell: Cell] RETURNS [a, b: REF ANY];

END.