; MesaGateEIAChain.mu -- Top-level microcode source for Alto Gateway
;			running Mesa and using EIA board and
;			3 copies of Chained Ethernet microcode.

;	Last modified HGM May 13, 1980  11:34 PM, Upgrade to Mesa 6.
;	Last modified March 28, 1979  10:51 PM

#AltoConsts23.mu;


; Reset locations of the tasks to be started in the Ram.
;	0	Emulator
;	1	Ethernet 2
;	2	Ethernet 1
;	7	Ethernet 0 (standard)
;	10	Memory Refresh task
;	11	Display Word task
;	12	Cursor task
;	13	Display Horizontal task
;	14	Display Vertical task

!17, 20, Emulator, 2EREST, 1EREST, , , , , 0EREST,
	MRT, DWT, CURT, DHT, DVT;

;
;	Now bring in Mesa overflow microcode  (From XMesaOverflow.mu)
;

#XMesaRAM.mu;

;-----------------------------------------------------------------
; MISC - Miscellaneous instructions specified by alpha
;	alpha=11 => RCLK has been handled by ROM
;	T contains alpha on arrival at MISC in RAM
;-----------------------------------------------------------------

; Precisely one of the following lines must be commented out.

MISC:		L_0, SWMODE, :Setstkp;			dummy MISC implementation

;#MesaMisc.mu;						real implementation

; Ram entry vector, for access via Mesa JRAM instruction.
; Note that only Ram locations 400-777 and 1400-1777 are reachable from Rom1.

%7, 1777, 1400, SilentBoot, EnableEIA, PupChecksum;


; Reserve 774-1003 for Ram Utility Area.
; These are assigned below to otherwise unlabelled instructions executed
; only by the Emulator task.

%7, 1777, 774, RU774, RU775, RU776, RU777, RU1000, RU1001, RU1002, RU1003;

; For the moment, just throw these locations away.  This is done only
; to squelch the "unused predef" warnings that would otherwise occur.
; If we ever run short of Ram, assign these to real instructions somewhere
; in microcode executed only by the Emulator.

RU774:	NOP;
RU775:	NOP;
RU776:	NOP;
RU777:	NOP;
RU1000:	NOP;
RU1001:	NOP;
RU1002:	NOP;
RU1003:	NOP;



; **** Modified standard tasks ****

#EIADispMRT.mu;		Memory refresh task -- interval timer and
;			cursor processing removed
#GateDisplay.mu;	Display and cursor tasks using 2 fewer R registers
;			than the standard microcode


; **** EIA microcode ****

#AltoEIA1.mu;		Only main dispatch, subroutines, and BiSync interface

; Suppress "unused predef" warnings caused by not including AltoEIA2.mu.
; If we ever run short of Ram, assign these to real, otherwise unlabelled
; instructions elsewhere.
RCAAT:	NOP;
TCAAT:	NOP;
TUIdl:	NOP;
TUBlk:	NOP;
EPRet2:	NOP;
ESRet2:	NOP;
ESRet3:	NOP;
EPRet3:	NOP;


; **** Chained Ethernet microcode ****

; Standard Ethernet board
$0ECNTR	$R12;		Standard R-registers
$0EPNTR	$R13;
$0ELOC	$600;		Standard control block address (600-611)
#ChainEther0.mu;

; First extra Ethernet board
$1ECNTR	$R11;		Same as CLOCKTEMP, which has been abolished
$1EPNTR	$R14;		Not used by Mesa or Nova emulator
$1ELOC	$630;		Control block address (630-641)
#ChainEther1.mu;

; Second extra Ethernet board
$2ECNTR	$R21;		Same as CURDATA, freed by special cursor microcode
$2EPNTR	$R26;		Same as HTAB, freed by special display microcode
$2ELOC	$642;		Control block address (642-653)
#ChainEther2.mu;



; **** Emulator Task ****

; Emulator, SilentBoot and PupChecksum
#PupChecksum.mu;


; EnableEIA: PROCEDURE[lineTab: POINTER]
; If lineTab is nonzero, specifies the address of the Line Table (LINTAB)
; and enables the EIA microcode.
; If lineTab is zero, disables the EIA microcode.
; Entry point is Ram address 1401.

!1, 2, EIAOn, EIAOff;

EnableEIA:
	L_ stkp-1;			stkp_ stkp-1
	stkp_ L, T_ 0+1;
	L_ stk0, BUS=0;			Get arg from stack, test for zero
	LINTAB_ L, :EIAOn;		[EIAOn, EIAOff]
EIAOn:	L_ R37 OR T, TASK, :UpdR37;	Nonzero, turn on R37[15]
EIAOff:	L_ R37 AND NOT T, TASK;		Zero, turn off R37[15]
UpdR37:	R37_ L, :Emulator;		Update R37