; MesaGateCPChain.mu -- Top-level microcode source for Alto Gateway running
;		    Mesa, CommProc and 2 Chained Ethernets.

;	Last modified HGM June 30, 1980  5:40 PM, Upgrade to Mesa 6.
;	Last modified HGM March 19, 1979  12:13 PM


#AltoConsts23.mu;


; Reset locations of the tasks to be started in the Ram (Emulator, MRT,
; CommProc, Interval Timer, and one extra Ethernet).
; Extra Ethernet is assumed to be run by task 2.
;	0	Emulator
;	1	CP Interval Timer -or- Ethernet 2.
;		Note: if Ethernet 2 is actually to be used, the interval timer 
;		wakeup and active signals must be disconnected.
;	2	Ethernet 1
;	6	CommProc
;	7	Ethernet 0 (standard)
;	10	Memory Refresh task
;	11	Display Word task
;	12	Cursor task
;	13	Display Horizontal task
;	14	Display Vertical task

!17, 20, Emulator, IntTimerTask, 1EREST, , , , CommProcTask, 0EREST, MRT, DWT, CURT, DHT, DVT;


; Ram entry vector, for access via Mesa JRAM instruction.
; Note that only Ram locations 400-777 and 1400-1777 are reachable from Rom1.

%7, 1777, 1400, SilentBoot, SetLineTab, PupChecksum, ChangeControlReg;


; Reserve 774-1003 for Ram Utility Area.

%7, 1777, 774, RU774, RU775, RU776, RU777, RU1000, RU1001, RU1002, RU1003;

; For the moment, just throw these locations away.  This is done only
; to squelch the "unused predef" warnings that would otherwise occur.
; If we ever run short of Ram, assign these to real instructions somewhere
; in microcode executed only by the Emulator.

RU774:	NOP;
RU775:	NOP;
RU776:	NOP;
RU777:	NOP;
RU1000:	NOP;
RU1001:	NOP;
RU1002:	NOP;
RU1003:	NOP;


;
;	Now bring in Mesa overflow microcode  (From XMesaOverflow.mu)
;

#XMesaRAM.mu;

;-----------------------------------------------------------------
; MISC - Miscellaneous instructions specified by alpha
;	alpha=11 => RCLK has been handled by ROM
;	T contains alpha on arrival at MISC in RAM
;-----------------------------------------------------------------

; Precisely one of the following lines must be commented out.

MISC:		L_0, SWMODE, :Setstkp;			dummy MISC implementation

;#MesaMisc.mu;						real implementation



; **** Modified Memory Refresh Task ****

#CPDispMRT.mu;		Memory refresh task -- interval timer and
;			cursor processing removed
#GateDisplay.mu;		Display and cursor tasks using 2 fewer R registers
;			than the standard microcode


; **** CommProc microcode ****

#CommProc1.mu;		Main Dispatch, subroutines and BiSync interface
#CommProc2.mu;		Uniterpreted & Char-at-a-time interfaces, interval timer.


; **** Chained Ethernet microcode ****

; Standard Ethernet board
$0ECNTR	$R12;		Standard R-registers
$0EPNTR	$R13;
$0ELOC	$600;		Standard control block address (600-611)
#ChainEther0.mu;

; First extra Ethernet board
$1ECNTR	$R11;		Same as CLOCKTEMP, which has been abolished
$1EPNTR	$R14;		Not used by Mesa or Nova emulator
$1ELOC	$630;		Control block address (630-641)
#ChainEther1.mu;

; **** Emulator Task ****

; Emulator, SilentBoot and PupChecksum
#PupChecksum.mu;


; SetLineTab: PROCEDURE[lineTab: POINTER]
; Specifies the address of the Line Table (LINTAB).
; Entry point is Ram address 401.

SetLineTab:
	L_ stk0;			LINTAB_ top of stack
	LINTAB_ L;
	L_ 0, TASK;			Empty the stack
	stkp_ L, :Emulator;


; ChangeControlReg: PROCEDURE[lineTimes4: CARDINAL, changeMask: WORD]
; Changes (sets or resets) bits in the control word for a line.
; The change is atomic with respect to CommProc task execution.
; lineTimes4: 4 times the line number to be affected.
; changeMask: Bits 4:15 are a mask of bits to be affected and bit 0 is
;	the desired new value of those bits.

ChangeControlReg:
	L_ 0, TASK;			Empty the stack (TASK vital here)
	stkp_ L;
	L_ stk0;			lineTimes4
	LINE*4_ L;
	T_ stk1;			T_ changeMask
	L_ LCRetX#, :LIMCon0;		L_ LIMCon0 return index
LCRetX:	:Emulator;