ER[DGMR];	*RANDOM NO. TEST FOR MAIN MEMORY TO FIND BAD CHIPS

%TO ASSEMBLE:	MICRO/L LANG DGMR
TO RUN:		MIDAS RDGMR
		SET "MLOW" AND "MHIGH" TO BRACKET THE MEMORY REGION
		SET "RLOOK" (READS) AND "WLOOK" (WRITES) TO CAUSE "SIGNOVA"
		SET "AINC" TO THE ADDRESS INCREMENT
		START;G

"DGMR" TESTS SEQUENTIAL ADDRESSES FROM "MLOW" TO "MHIGH" USING RANDOM
DATA IN TOP 36 BITS AND COMPLEMENT OF THAT IN LOW 4 BITS.  "SIGNOVA"
IS GENERATED ON WRITES WHEN "WLOOK" = "ADDR" AND F2[3] ON READS WHEN
"RLOOK" = "ADDR".  "MASK" AND "MASKL" DETERMINE THE BITS CHECKED ON
DATA COMPARISON.  AT ERRORS, "MAR" CONTAINS THE ADDRESS, "MDR" AND "MDRL"
THE DATA READ, AND "DATA" AND "DATAL" THE EXPECTED DATA VALUES.
WHEN "AINC" # 1, BE SURE THAT "MHIGH" POINTS TO THE LARGEST ADDRESS
ACTUALLY WRITTEN (NOT IN THE GAP BETWEEN ADDRESSES).

"DGM" SHOULD WORK BEFORE THIS IS TRIED.

THE NORMAL ENTRY "START" USES THE PROCESSOR MEMORY INTERFACE FOR TESTING.
ALTERNATE ENTRY "KSTART" USES THE DISK MEMORY INTERFACE FOR TESTING.
%

SM[SLC,20]; RM[RLC,0]; LM[LLC,10];

RV[X0,7654321];
RV[X1,76543210];
RV[X2,765432100];
RV[X3,7654321000];
RV[X4,76543210000];
RV[X5,765432100000];
RV[X6,654321000007];
RV[X7,543210000076];

LVN[RAN]; LVN[RRAN]; LVN[XRAN]; LVN[COUNT];

LVN[DATA]; LV[MASK,777777 777777]; RVN[DATAL]; RV[MASKL,17];
LV[WLOOK,10000000]; LV[RLOOK,10000000];
LV[MHIGH,777777]; LV[MLOW,0]; SVN[ADDR]; SVN[COUNT]; RV[AINC,1];

TARGET[ILC];

REPEAT[20,ILC[(BRKP[1]FRZBALUBC)]];

MCYCLE:	BRKP[1], Q_P+1, RETURN;

START:	COUNT_ARM_NULL, INHINT;
	IRET, INHINT, CALL[INIRAN];
	Q_COUNT, GOTO[LOOP];

PQZT:	P AND Q, GOTO[.+2];
PQCOMP:	P#Q;
	RETURN[ALU=0];
	BRKP[1], RETURN;

RETN:	RETURN;

*INITIALIZE RANDOM NO. GEN.
INIRAN:	DGOTO[7], Q_X7;
	X_NPC, RAN_Q, RETURN;

*SAVE RANDOM NO. GEN. STATE IN LM FOR RESTORATION LATER
RMARK:	P_X, DGOTO[7], Q_RAN;
	X_NPC, GOTO[.+1], RRAN_Q;
	Q_RX, GOTO[.+2,X<0], XRAN_P;
	LX_Q, DECX, GOTO[.-1];
PXRET:	X_P, RETURN;

*RESTORE RANDOM NO. GEN FROM LM
RREST:	P_RRAN, DGOTO[7];
	X_NPC, RAN_P, GOTO[.+1];
	Q_LX, GOTO[PXRET,X<0];
	RX_Q, P_XRAN, DECX, GOTO[.-1];

*SEQUENCE THAT USES PROCESSOR'S MEMORY INTERFACE FOR TESTING.
LOOP:	COUNT_Q, CALL[RGEN];
	Q_MLOW;
	ADDR_Q, CALL[RMARK];	*SAVE INITIAL STATE OF RANDOM NO. GEN.
	CALL[RGEN];
WRANM:	MDR_Q, DATAL_NOT Q;
	WRITE_Q_ADDR, P_WLOOK, INHINT;
	P#Q, Q_DATAL, INHINT;
	MDRL_Q, GOTO[.+2,ALU#0];
	SIGNOVA, P_ADDR, Q_MHIGH, GOTO[.+2]; *SCOPE TRIGGER FOR ADDR=WLOOK
	P_ADDR, Q_MHIGH;
	P-Q, Q_AINC;
	Q_P+Q, DGOTO[WRANM,ALU<0];
	ADDR_Q, CALL[RGEN];

*NOW READ AND COMPARE
	Q_MLOW;
	ADDR_Q, CALL[RREST];
	CALL[RGEN];
RRANM:	DATA_Q;
	READ_P_ADDR, DATAL_NOT Q, Q_RLOOK;
	P#Q, Q_MHIGH;
	P-Q, Q_AINC, GOTO[.+2,ALU#0];
	FRZBALUBC, F2[3];	*SCOPE TRIGGER FOR ADDR=RLOOK IS F2[3]
	Q_P+Q, DGOTO[RRANM,ALU<0];
	ADDR_Q, CALL[.+3];
	DGOTO[LOOP];
	P_COUNT, CALL[MCYCLE];
	Q_MDR, P_DATA;
	P_P#Q, Q_MASK, CALL[PQZT];	*TOP 36 BITS WRONG
	Q_MDRL, P_DATAL;
	P_P#Q, Q_MASKL, CALL[PQZT];	*LOW 4 BITS WRONG

*RETURN RANDOM NO. IN Q (USES X WHICH MUST NOT BE CLOBBERED), CLOBBERS P
RGEN:	P_RAN, Q_RX, GOTO[RGEN1,X>=0];
	DGOTO[6], Q_X7;
	X_NPC, RAN_X7_Q_P+Q, RETURN;

RGEN1:	RX_RAN_Q_P+Q, DECX, RETURN;

*SEQUENCE THAT USES THE DISK MEMORY INTERFACE FOR TESTING.

KSTART:	COUNT_ARM_NULL, INHINT;
	IRET, INHINT, CALL[INIRAN];
	Q_COUNT, GOTO[KLOOP];

KLOOP:	COUNT_Q, CALL[RGEN];
	Q_MLOW;
	ADDR_Q, CALL[RMARK];	*SAVE INITIAL STATE OF RANDOM NO. GEN.
	CALL[RGEN];
KWRANM:	MDR_Q, DATAL_NOT Q;
	WRITE_Q_ADDR, P_WLOOK, INHINT;
	P#Q, Q_DATAL, INHINT;
	MDRL_Q, GOTO[.+2,ALU#0];
	SIGNOVA, P_ADDR, Q_MHIGH, GOTO[.+2]; *SCOPE TRIGGER FOR ADDR=WLOOK
	P_ADDR, Q_MHIGH;
	P-Q, Q_AINC;
	Q_P+Q, DGOTO[KWRANM,ALU<0];
	ADDR_Q, CALL[RGEN];

*NOW READ AND COMPARE
	Q_MLOW;
	ADDR_Q, CALL[RREST];
	CALL[RGEN];
KRRANM:	DATA_Q;
	READ_P_ADDR, DATAL_NOT Q, Q_RLOOK;
	P#Q, Q_MHIGH;
	P-Q, Q_AINC, GOTO[.+2,ALU#0];
	FRZBALUBC, F2[3];	*SCOPE TRIGGER FOR ADDR=RLOOK IS F2[3]
	Q_P+Q, DGOTO[KRRANM,ALU<0];
	ADDR_Q, CALL[.+3];
	DGOTO[KLOOP];
	P_COUNT, CALL[MCYCLE];
	Q_MDR, P_DATA;
	P_P#Q, Q_MASK, CALL[PQZT];	*TOP 36 BITS WRONG
	Q_MDRL, P_DATAL, DGOTO[RGEN];
	P_P#Q, Q_MASKL, CALL[PQZT];	*LOW 4 BITS WRONG