ER[LOADER];

%CURRENT SOURCES SHOULD ALWAYS BE FOUND ON <ERF>LOADER.MC.

TO ASSEMBLE:	MICRO DLANG2 LOADER

THE ONLY STORAGE ASSEMBLED IS FOR THE DUMMY MEMORY CALLED "LDR", AN
ARTIFACT OF MIDAS.  THE 80-BIT INSTRUCTIONS IN THIS MEMORY ARE EXECUTED
THROUGH THE MAXC2 ALTO'S MAINTENANCE INTERFACE, WHERE THE SEQUENCE OF
OPERATIONS IS AS FOLLOWS:

	FOR I = 0 TO 3 DO
	[ @ADREG = table [ PIR0; PIR1; PIR2; PIR3 ] !I
	  @OUTREG = INST!I
	]
	@ADREG = CR; @OUTREG = not INST!4

NOTE THAT THE LAST WORD (CONTROL BITS) IS COMPLEMENTED.

AFTER EXECUTION (EXCEPT FOR THE "RUN" INSTRUCTION), ANY VALUE PUT ON THE
BUS CAN BE READ BY THE ALTO AT LEISURE BY THE FOLLOWING SEQUENCE:

	@ADREG = B0; REGVAL!0 = not @INREG
	@ADREG = B1; REGVAL!1 = not @INREG
	@ADREG = B2; REGVAL!2 = ((not @INREG) lshift 4) & 170000B

TO LOAD A REGISTER FROM THE ALTO, THE FOLLOWING SEQUENCE:

	@ADREG = BR0; @OUTREG = not REGVAL!0
	@ADREG = BR1; @OUTREG = not REGVAL!1
	@ADREG = BR2; @OUTREG = (not REGVAL!2) rshift 4
	execute the instruction to load the register

NOTE THAT THE DATA IS UNIFORMLY COMPLEMENTED AND THAT THE VALUE FOR BUS
BITS 32-35 IS OUTPUT IN ALTO WORD BITS 4-7.
%

*CURRENT SOURCES SHOULD ALWAYS BE FOUND ON <ERF>LOADER.MC

SM[SMFORF,377];	*SM REGISTER FOR SETTING FLAGS

TARGET[LDRLC];

%MANIFEST CONSTANTS IN MX.D ASSUME THE LOCATIONS OF THE FIRST GROUP
OF INSTRUCTIONS.  ***DO NOT REORDER WITHOUT FIXING MANIFEST CONSTANTS***
%

	B_X, EIC[0];
	B_AC, EIC[0];
	B_Y, EIC[0];
	B_P, EIC[0];
	B_Q, EIC[0];
	B_FLAGS, EIC[0];
	B_NPC, EIC[0];
	B_MAR, EIC[0];
	B_MDR, EIC[0];
	B_MDRL, EIC[0];
	B_KMAR, EIC[0];
	B_KMDR, EIC[0];
	B_KMDRL, EIC[0];
	B_ARM, EIC[0];
	B_KUNIT, EIC[0];
	B_EREG, EIC[0];
	B_BPC, EIC[0];
	CALL;
	B_STACK, EIC[0];
	POP, B_NPC;
	B_NPC, ENPC[1];
	NPC_BR, ENPC[1], EIMA[1];
	P_P1, B_P;
	EIC[0], SETRUN[0], RESET[0], REGTOB[1];

	X_BR;
	AC_BR;
	Y_BR;
	P_BR;
	Q_BR;
	SETF[SMFORF], Y_BR;
	NPC_BR, ENPC[1];
	READ_BR;
	MDR_BR;
	MDRL_BR;
	KREAD_BR;
	KMDR_BR;
	KMDRL_BR;
	ARM_BR, RETURN[NEVER], T[37];	*KLUDGES TO FORCE CORRECT IM PARITY
	KUNIT_BR;
	B_BR;
	BPC_BR;
	B_SMFORF, EIC[0];
	SMFORF_Q;
	CLEARF[SMFORF], Y_BR;
	SETF[SMFORF], Q_BR;
	CLEARF[SMFORF], Q_BR;
	SETF[SMFORF], Q_NOT Q;

	Q_LX, B_Q;
	Q_RX, B_Q;
	B_MAP;	*CANNOT HAVE EIC=0 HERE OR PARITY WON'T BE CHECKED
	B_D;
	B_D1;
	B_D2;
	B_SY;
	I;
	I, INHINT;
	B_KSTAT, EIC[0], INHINT;

	LX_Q;
	RX_Q;
	MAP_Q;
	D_Q;
	D1_Q;
	D2_Q;
	SY_Q;
	I_EREG;
	I_EREG, INHINT;

	ARM_NULL, INHINT;
	IRET, INHINT;

	FRZBALUBC, XPIR[0], EB[1], ENPC[1], EIMA[1];
	FRZBALUBC, XPIR[0], EB[1], ENPC[1], EIMA[1], INTON[1], NOTSS[1];
	FRZBALUBC, XPIR[0], EB[1], ENPC[1], EIMA[1], INTON[1];
	WRESTART, KWRESTART;

*FIELDS FOR INITIALIZING LDR WORDS USED AS DATA
F[ED0,104,117]; F[ED1,70,103]; F[ED2,54,67];
F[ED3,40,53]; F[ED4,24,37]; F[ED5,10,23]; F[ED6,0,7];

CONFIG:	ED6[0] ED5[0] ED4[0] ED3[0] ED2[70] ED1[700] ED0[7007];
BITS-CHECKED: ED6[0] ED5[0] ED4[0] ED3[0] ED2[7777] ED1[7777] ED0[7777];
DATA-WAS: ED6[0] ED5[0] ED4[0] ED3[0] ED2[0] ED1[0] ED0[0];
SHOULD-BE: ED6[0] ED5[0] ED4[0] ED3[0] ED2[0] ED1[0] ED0[0];
LOW-HIGH: ED6[0] ED5[0] ED4[0] ED3[0] ED2[0] ED1[0] ED0[7777];
LOOP-COUNT: ED6[0] ED5[0] ED4[0] ED3[0] ED2[0] ED1[0] ED0[0];
	ED6[0] ED5[0] ED4[0] ED3[0] ED2[0] ED1[0] ED0[0];

*NO-OPERATION INSTRUCTION FOR USE WITH FIELD-SELECT TESTS
	EIC[1];

%THE INSTRUCTIONS BELOW ARE USEFUL FROM MXTST.BCPL BUT NO MANIFEST
CONSTANTS REFER TO THEM, SO IT IS OK TO REORDER AND CHANGE THEM.
%

*INSTRUCTION TO PRODUCE ALL ONES ON THE BACKPANEL FOR THE INSTRUCTION
*SIGNALS COMING OUT OF THE PMAINT CARD.
	BT[3] C[37] LA[37] RA[37] PS[77] QS[7] A[37] O[37] T[37] Z[77]
	F2[17] SA[377] SCP[1] EIC[0] EB[0] EIMA[0] ENPC[0] NOTSS[0]
	SETRUN[0] RESET[0] XPIR[1] REGTOB[0] INTON[0] STROBE[0];

*INSTRUCTION TO PRODUCE ALL ZEROES ON THE BACKPANEL FOR INSTRUCTION
*SIGNALS OUT OF PMAINT
	BT[0] C[0] LA[0] RA[0] PS[0] QS[0] A[0] O[0] T[0] Z[0]
	F2[0] SA[0] SCP[0] EIC[0] EB[0] EIMA[0] ENPC[0] NOTSS[0]
	SETRUN[0] RESET[0] XPIR[1] REGTOB[0] INTON[0] STROBE[0];