TIMING CONSIDERATIONS FOR MAXC2


The cycle time of the machine is denoted by C and constraints on clocks are derived by worst case and observed measurements.  All times are in nanoseconds.

The analysis assumes bus data from slow sources (ALU, bipolar memories, FLAGS, etc.) and all other inputs to multiplexors receiving bus data are good at C.

Low true clock names begin with "-K", high true with "K".  Some clocks, such as KD, KA, and KIMA are "early" (relative to 0).  Others, such as KBF, KBS, -K3, -K2, -K1, and KEBL are "late" (relative to C).

Clock ranges refer to the "true" period.  For example, KBF is "high true", so KBF = -100 to +15 means it is high from C-100 to C+15.  Similarly, -K1 = -10 to +15 means it is low during that period.


SIGNAL DELAYS

Several copies of a clock may be derived on MISC to limit delay from earliest use to latest or to improve signals.  Variations may be enabled differently or be delayed, advanced, or widened.

Standard usage receives a clock with a typical H04 on a card (delay 5 to 7).  Other components in clock paths are also typical to limit skew.

Wire propagation time assumed 1.5/foot.

Net capacity is computed as follows:
	Wire adds 15 pf/foot;
	Components add 6 pf/pin unless specified differently;

(5-V)*Isc/5 of a device is the drive for charging capacity.  Initially this is supplemented by the load current, which becomes negligible after charging to .4 volts.  Isink discharges capacity.

Hence, a device like an H04 or H00, with Isink = 30 ma and Isc = -50 ma, averages 42 ma charging load capacity from 0.2 to 1.4 volts and 30 ma discharging from 4.5 to 1.4 volts.  A heftier device like an H40 with Isink = 60 ma and Isc = -60 ma averages -50 ma charging and 60 ma discharging.

For calculation purposes, capacitive delay is assumed 1*C/Isc for output going low to high and 3*C/Isink for output going high to low, where C is pf, I ma.  This results in the following corrections, where the device spec. is assumed to be for a 30 pf load:

Net Capacity	     Hefty		     Ordinary
		Down	Up	Down	Up

    60 pf		1.5	0.5	3.0	0.6
    90 pf		3.0	1.0	6.0	1.2
   120 pf		4.5	1.5	9.0	1.8

SUMMARY OF CLOCK USAGE

Clock	Places	Uses

-K1	MICONT	Assorted memory clocking
	DECODE	Latches -FASTCUM, -FASTJ
	PMEMI	-K1+H04+H00 clocks S174's whose input is -B[xx]+N368 or -D[xx]+8T26
	KMEMI	-K1+H04+H00 clocks S174's whose input is -B[xx]+8T26 or -D[xx]+8T26
	MISC	-K1+H00+H08 clocks -NOEXA and MEMPE H108's
-K1IC	YINT	-K1IC+H04+H04 latches -B[xx](etc.)+F9312
	COND	-K1IC+H04+H04 clocks -NEWG (etc.)
	XACRL	-K1IC+H04+H04 latches -B[xx](etc.)+F9312
	STACK	-K1IC+N28+N28 clocks N194's whose input is -B[xx]+I3404
-K1IC*	MICONT	-K1IC*+H04+H00 clocks H74's for (K)FETCH and (K)STORE
	PMEMI	-K1IC*+H04+H00 clocks S174's whose input is MAP[xx]+N367 or -B[xx]+8T26
	KMEMI	-K1IC*+H04+H00 clocks S174's whose input is -B[xx]+8T26
	MAINF	-K1IC*+H08+N28 clocks N279's whose input is S[xx]+LSxx
-K1ICE	ALUA	-K1ICE+M3002+M3002 latches Q[xx]
K1ICE	COND	K1ICE+H00 (slow) is write enable for LM/RM 3101A's
KP	ALUB	KP+H04 latches P[xx]
-KP	ALUB	latches P[12] and P[24]
-KP0	ALUB	latches P[0]
KNPC	CONTROL	KNPC+H00 latches -NPC
KBL	BEB	KBL+H04 latches -B[24,35]+S04 for NPC

KEBL	COMCON2/3	KEBL+H04 latches -EB[0,35] for disk stuff and IM read/write
KEBLP	BEB	= KEBL+H08.  Latches bus parity for IM write

-KW	MAP	-KW+H04+H00 clocks 3107A's
	SM/DM
-KWIM	IM	-KWIM+H04+H00 clocks 3107A's

-K2	YINT	-K2+H04 latches second rank of Y[xx]
	COND	-K2+H04 latches ALUZTEST, -OLDALU0, Y<=44 and CYCY
	XACRL	-K2+H04 latches second rank X[xx]
	MISC	-K2+H04 latches ALUC0 and -ALUF0
-K2*	ALUB	-K2*+H04 latches second rank P[xx], -K2*+H04+H04+H04 latches ALU
	ALUA	-K2*+H00 latches second rank Q[xx]

-K3	YINT	-K3 latches INT and INT*, -K3+M3003 latches INTIR and IA[xx]
-K3IC	CONTROL	-K3IC+N28+N28 clocks N194's on STACK
	COMCON2/3	-K3IC+H04+H00 clocks buffer1 3101A's
	COMCON2/3	-K3IC+M3002+H00 clocks buffer2 3101A's
KBST	CONTROL	KBST+H04 latches S258 selects and 8T10 output disables, clocks 8T10's
	MISC	KBST+H04 latches IMREF for -NOEX

KA	MICONT	KA+H04 latches destinations and slow sources
	DECODE	KA+H04 latches destinations and slow sources, -PQCTL[x], MAPA[26]L
	MAP	KA+H00 latches addresses and selects for 3107A's
	MAINF	KA+H04 latches IBT[x] and -IBA[xx] for BAT
	MISC	KA+H04 latches FDORUN and IQSEL[x]
KA*	SM/DM	KA*+H00 latches addresses and selects for 3107A's
	YINT	KA*+H08 latches -NEWINTOK
	XACRL	KA+H04 latches xMASK, BAT xX multiplexors
-KPE	BEB	-KPE+H00+H40 latches bipolar parity

KSTK	CONTROL	KSTK+H00 latches STACK mode controls
KIMA	4 IM	KIMA+H00 latches addresses and selects for 3107A's
	CONTROL	KIMA+H00 latches BRL and IMAX[25] and clocks IMA N175's
KIMA*	4 IM	KIMA+H00 latches addresses and selects for 3107A's
-KNPCSEL	CONTROL	-KNPCSEL latches DOINT, WANTKNPC, S258 selects, and 8T10 output disables

KBF	PMEMI	KBF+H04+N28 enables B_MDR, B_MDRL, and B_MAR
	KMEMI	KBF+H04+N28 enables B_KMDR, B_KMDRL, and B_KMAR
	YINT	KBF+H04+N28 enables B_Y
KBF*	XACRL	KBF*+H00+M3002 (= -K_Q+M3002) enables B_Q,
		KBF*+H04+N28 enables B_X and B_AC
	STACK	KBF+H04+N28 enables B_STACK and B_NPC
KEBF	COMCON2/3	KEBF+M3002+M3002 and KEBF+M3002+H11+M3002 enable various N38's

KBS	COND	KBS+H04+N28 enables B_FLAGS
	XACRL	KBS+H04+N28 enables B_BAT
	BEB	KBS+H04+H04+H00 enables B_EB, B_ARM, and B_BPC
KBS*	MAP	KBS*+M3026 enables N38's
	SM/DM	KBS*+M3026 enables N38's
	MAINF	KBS*+H04+N28 enables B_FLAGS
-KALU	ALUA	-KALU+H00 enables ALU N38's
KBEB	BEB	KBEB+H00 enables EB_B
KBSI	IM	KBSI+M3026 enables EB_IM N38's

KI	CONTROL	KI+H04 latches -IBA[xx]
	DECODE	KI+H04 latches CARRY1
	COMCON2/3	Selects buffer 2 contents in anticipation of KRDATA
KI*	COND	KI+H04 latches IPSEL[xx]
	XACRL	KI+H04 latches IAF[x]
KD	MICONT	KD+H04 latches fast sources
	DECODE	KD+H04 latches fast sources

KDR	PMAINT	KDR+H08 clocks S112 for RUN1; KDR+H04 clocks RUN N174's

-NOEX	MISC	Produces -NOEXA/B, enables DOIBREAK
	DECODE	Enables -LOADPC
	YINT	enables -IR
	CONTROL	forces no-branch

-NOEXA/B	MISC	enables -KW, -KWIM, -K1IC, -K1IC*, K1ICE, -K1ICE, KEBL

RUN1	MICONT	enables FDORUNx

BUS DATA

Bus electrical properties are of interest because large capacitance and moderate noise cause signals to develop slowly.  The most constraining events are bipolar memory write and E-bus write from a "fast" bus source, bus write from the E-bus, and bus write from the "slow" ALU or bipolar memory sources.

The bus is pulled toward 3 volts by 220-ohm pullup, 330-ohm pulldown resistors on the BEB card.  Pullup resistors are small to charge the bus high quickly.  Pulldown resistors limit high voltage to 3 volts, so drivers will pull low quickly.

Bus clocks disable sources at the end of a cycle to charge the bus high until new source data and enable are ready.  This is desirable because the bus can be driven low faster than high.

In most places, bus drivers are open-collector N38's sinking -48 ma.  Tristate 8T26A's sinking -50 ma are used for MAR, MDRL, KMAR, KMDR, and KMDRL.  E-bus is driven onto the bus by tristate 8T97's sinking -40 ma.

Bus clocks are KBF (N38 and 8T26A fast sources) and KBS (slow sources or E-bus sources).  Standard use is KBF+H04+N28 enabling drivers.

Exceptions:  Bipolar card N38's are enabled by KBS+MC3026 (new cards by KBS+H00+H40), Q by KBF+H00+M3002, ALU by KBS+H00+H00, BEB 8T97's by KBS+H04+H04+H00.

KBFd must be late enough for all places receiving bus data to be finished with it.  Receivers latch or clock bus data under control of -K1IC, or the MAP and SM/DM cards write data under control of -KW.

KBSd is constrained only by -K1IC because slow sources cannot be used in conjunction with a bipolar write.

The time at which the bus starts to pull high is governed by the high-Z time of the driving devices, as follows:  N38's 22; 8T09's 14; 8T26A's 20; 8T97's 12; 8T98's 16.

KBS+H04+H04+H00 enabling 8T97's and 8T98's on BEB is equivalent to KBS+H04+N28 standard usage because 8T97's and 8T98's are faster than N38's.

KBF^+H04 is desired as soon as the bus source decoding is finished.

Observed timing of -B[35] is as follows:

	bus good = max(KBFd+70,KBF^+45+C) to min(KBFd+35+C,KBF^+22+2C). 

This implies KBS^ < -45 to get valid bus data by C.

Heaviest bus loading are -B[32,35] received by:  1 S04 (BEB), 2 F9309's (AC and P), 3 F9312's (X, Y, and Q), 2 I3404's (STACK and ARM), 2 H08's (old bipolar SM/DM and MAP) or 2 8T93's (new bipolar), 5 8T26A's (MAR, MDRL, KMAR, KMDR, and KMDRL), and 1 N368 (MDR).  F9309's, F9312's, H08's, and 8T26A's don't use much current unless the bus input is selected, so worst case for devices is about -9 ma (bus low) plus -22.7 ma for the pullup = -32 ma.  Actual device current is probably about -4 ma at 0.3 volts, so pullup resistors could be smaller.  -B[32,35] are driven by 12 N38's and the 8T09 on BEB, in addition to the 8T26A's which serve as both drivers and receivers.

Lightest bus loading is -B[12] received by:  1 S04 (BEB), 2 F9309's (P and AC), 1 F9312 (Q), 1 I3404 (STACK), 1 H08 (old bipolar SM/DM) or 1 8T93 (new SM/DM), 2 8T26A's (KMDR and MDR).  Worst case is about -9 ma for these plus -22.7 ma for the pullup = -32 ma total.  -B[12] is driven by 6 N38's and an 8T09 on BEB.

**Afterthought:  More even distribution of bus load would have been desirable--mainly move stuff from -B[32,35] to other bits.  Connecting MDRL and KMDRL to -B[0,3] instead of -B[32,35] would have been one way to accomplish this.

The register driving the bus should have good data until KBFd shuts it off and must have (new) good data before KBF enables its bus drivers in the next cycle.  It must not have any short paths back to the input.

I3404 latches change during -K1IC, so second rank I3404's clocked by -K2 keep old data valid for X, AC, Y, P, Q, and ALU (ALU discussed later).  This means:
	-K2d+H04+I3404hold < -K1ICd+9+I3404clock (= -K1ICd > -K2d+4) for P
	KBF^+H04+N28+C > -K2^+H04+I3404clock (= KBF^+C > -K2^+13) for X, Y, AC, P, Q
	KBF^+H04+N28+C > -K1ICd+16+I3404clock+I3404data (= KBF^+C > -K1ICd+34) for Q
	KBFd+H04+N28 < -K2^+H04+I3404clock (= KBFd < -K2^+3) for X, Y, AC, Q
	-K1IC^+10+I3404hold-F9309-H04-N283 < -K2^+H04+I3404clock (= -K1IC^ < -K2^+12) for X, AC
	-K1IC^+18+I3404hold < -K2^+H00+I3404clock+H04+F9312 (= -K1IC^ < -K2^-3) for Q

The -K2 H04 for P and ALU has about a 10-12 delay due to heavy loading.

For S174's the constraint is:
	KBF^+H04+N28+C > -K1IC^+S174data (= KBF^+C > -K1IC^+6)

It is illegal to drive the bus from STACK in the instruction after loading it from the bus, so there is no special constraint for the N194's on STACK.  NPC is analyzed in the CONTROL section.

At the receiving end, storage devices are I3404's with 12 setup, 8 hold; N194's 20 setup, 0 hold; S174's 12 setup, 0 hold; N175's 20 setup, 0 hold.    For I3404's, clockd should occur about 5 before data-good because max. latch delay is 17 from clockd but only 12 from data.  Other storage devices load on -K1IC^, wanted as soon after -K1ICd as is consistent with setup time.  Standard clocking of the storage devices is -K1IC+H04+H00 (Variants of -K1IC are -K1IC*, -K1ICE, KBL, KP, -KP, -KP0, KNPC, etc.).

Receiving devices before I3404's are F9309's (6? to 15), and F9312's (6? to 16), where the faster false output of these is always used.  ARM has no device between the bus and its I3404, but only one gate delays -K1IC, so its timing constraints are similar.  I3404's and LS163's on BEB are preceded by S04's (3 to 5);  N194's on STACK by I3404's used as inverters (6 to 12); S174's on PMEMI by N368's (6? to 17); S174's on KMEMI by 8T26A's (6? to 18); N175's on COND by H53's (5 to 10).

These uses constrain -K1IC^ > max. of the following:

	I3404setup-M3003 = 12-5 =7 for ARM
	8T26Adata+S174setup-H04-N28 = 14+12-11 = 15 for KMDR, KMDRL, KMAR, MAR, MDRL
	N368data+S174setup-H04-N28 = 17+12-11 = 18 for MDR
	I3404data+N194setup-N28-N28 = 12+20-12 = 20 for STACK
	F9312+I3404setup-H04-H04 = 16+12-10 = 18 for X, Y, AC
	F9312+I3404setup-16 = 16+12-16 = 12 for Q
	F9309+I3404setup-2-H04 = 15+12-2-5 = 20 for P
	H53+N175setup-H04-H04 = 11+20-5-5 = 21 for NEWG
	S04+I3404setup-H04 = 5+12-5 = 12 for -LB
	S04+LS163setup-H04-H04 = 5+20-5-5 = 15 for BPC

Bus data must remain good until -K1IC^+ max. of the following:

	I3404hold+M3003 = 8+9 = 17 for ARM
	S174hold-8T26Adata+H04+N28 = 0-5+7+8 = 10 for KMDR, KMDRL, KMAR, MAR, MDRL
	S174hold-N368data+N28+N28 = 0-7+8+8 = 9 for MDR
	N194hold-I3404data+N28+N28 = 0-6+8+8 = 10 for STACK
	I3404hold-F9312+H04+H04 = 8-6+7+7 = 16 for X, Y, AC
	I3404hold-F9309+H04+1 = 8-6+7+1 = 10 for P
	I3404hold-F9312+16 = 8-6+16 = 18 for Q
	N174hold-H53+H04+H04 0-5+7+7 = 9 for NEWG
	I3404hold-S04+H04-3 = 8-3+7-3 = 9 for -LB
	LS163hold-S04+H04+H04-5 = 0-3+7+7-5 = 6 for BPC

Hence, min(KBFd+35,KBF^+22) > -K1IC^+17 (= min(KBFd+18,KBF^+5) >-K1IC^).

Viewed another way, late data from a slow source will most likely manifest as failure of STACK, MDR, X, Y, AC, P, or a branch condition; bus data bad too soon as failure of ARM, X, Y, AC, or Q.

**Using -K1ICE for ARM, narrowing clock for Q, and delaying STACK's clock by 4 would ameliorate timing.  A short path from new Q to P prevents delaying P timing, which would otherwise be helpful.

An inverted equivalent of -K1IC called K1ICE is used as write enable for 3101A's on ALUB which must be 25 wide, but K1ICE is 6 wider than -K1IC, so the constraint imposed by this is no worse than for N194's and N175's.


EBUS DATA

The E-bus is driven under control of KBSI (IM reads--discussed later), -B_BR (data from the Alto--not discussed), KEBF (COMCON sources), and KBEB (on BEB--source of data on the bus).  Like the bus, the E-bus is pulled toward 3 volts by 220-ohm pullup/330-ohm pulldown resistors on COMCON2/3.

All -EB signals are loaded and driven similarly.  Receivers are 4 H08's (old IM boards) or 4 8T93's (new IM boards), 1 I3404 (COMCON2/3), 1 8T97 (BEB), an F9309 or N157 (PMAINT), an 8T26 (PMAINT).  Worst case current is about -8 ma from these devices plus -22.7 ma from pullup resistors, so actual current is probably about -27 ma.

Each -EB signal is driven by an 8T98 (BEB), an 8T10 (PMAINT), 5 N38's (4 IM boards and 1 COMCON), and an 8T09 (COMCON).

8T10's on PMAINT sink only -32 ma, compared with -40 ma for the 8T09's and 8T98's and -48 ma for the N38's.  This means pullup resistors cannot be much smaller than the 220-ohm ones used.  (The slow turn-off time for 8T10's doesn't matter because they are only used from the Alto.)

The timing for -EB to pull from a low value to threshold is as follows:
  From BEB 8T98's:		KBEBd+** (min)		KBEBd+** (max)
  From COMCON2/3 8T09's:	KEBFd+** (min)		KEBFd+** (max)
  From IM N38's:		KBSId+** (min)		KBSId+** (max)

The max time for -EB to pull from a high value to threshold is as follows:
  From BEB 8T98's:		KBEB^+**
  From COMCON2/3 8T09's:	KEBF^+**
  From IM N38's:		KBSI^+**


BUS-EBUS CONNECTIONS

When -EB is driven from -B, KBEB^+H00 > max(KBFd+70,KBSd+70,KBS^+46)+S04-8T98enable+8T98delay-3 (= KBEB^+5 > max(KBFd+70,KBSd+70,KBS^+46)+5-12-5 = KBEB^ > max(KBFd+52,KBSd+52,KBF^+29) to ensure -B valid before driving -EB.  This crucial calculation allows a glitch of about 5 in the -EB output.  A glitch of about 10 is probably ok.

For EREG to receive data from -B, KEBLd+H04-I3404setup > max(KBEBd+**,KBEB^+**) = (KEBLd > max(KBEBd+**,KBEB^+**).  This is the early version of KEBL, a switched clock.

When -B is driven from -EB, KBS^+H04+H04+H00+8T97enable-8T97data > max(KEBFd+**,KBEBd+**,KEBF^+**), so -EB is good before driving -B.

-B_E should develop while KBEB is low (= KBEBd < KA^+H04+I3404clock =  KBEBd < KA^+12) and -B_E+H04 should develop while KBS+H04+H04 is low (= KBSd+7+7 < KA^+12 = KBSd < KA^-2).

EREG data is needed in time for driving -EB, so KEBF^+M3002+M3002+8T09enable-8T09data > max(KEBL^+H04+I3404clock,KBEB^+**+I3404data) (= KEBF^+6+6+22-10 > max(KEBL^+7+17,KBEB^+**) (= KEBF^ > max(KEBL^,KBEB^+**)).

-EB data from COMCON must be valid for IM writes and for driving -B.  The IM write constraint is given later.  The constraint for driving -B is max(KEBFd+**,KEBF^+**,KBEBd+**) < KBS^+H04+H04+H00+8T97enable-8T98delay+5 (= max(KEBFd+**,KEBF^+**,KBEBd+**) < KBS^+5+5+5+14-7+5 = ?).


SM/DM AND MP READ (old PC boards)

3107A's have valid direct outputs before max(60 after addresses A4, A5, A6, and A7 good, 40 after chip selects and addresses A0, A1, A2, and A3 good), and outputs remain valid until 5 after chip selects change or 15 after addresses change.  The heaviest loaded output S[35] is connected to 4 3107A's (9 pf), 1 N38 (6 pf), 1 390-ohm pullup (3 pf), H00 (6 pf), H08 (6 pf), H52 (6 pf), and 15 inches of wire (19 pf), for a total load of 82 pf, 390 ohms.  This probably slows the readout by 2 or 3 (ignored).

Address latches should be loaded as early as possible because read timing is tighter than write timing.

Chip addresses are ready at KA^+H00+I3404clock.  Chip selects then pass through H08's or MC3002's.  These develop slowly because of high capacity (used on 36 chips each).  We assume 11 to 17 delay through the address latches (even though they are typical), or 7 to 13 delay for the chip select latches and 9 to 15 through the MC3002 and H08.  Hence, addresses change between KA^+16 and KA^+24, chip selects between KA^+21 and KA^+35.  3107A direct outputs are valid from KA^+84 until C+KA^+27.

SM direct outputs were all observed valid by KA^+70 except for one invalid until KA^+77.  However, analysis below assumes KA^+84.

For MAP, addresses from Y are good by max(-K1IC+H04+H04+I3404clock,F9312+I3404data) (= max(-K1ICd+7+7+17,16+12 = max(-K1ICd+31,28).  -MAPA[26] is good by IMgood+I3205+H04+S64 (= IMgood+18+10+5 = IMgood+33).  Address latch write enables are not needed earlier than 5 before the inputs are valid because delay from write enable is 17, but only 12 from the data, so KA^+H00 > max(-K1ICd+31,28,IMgood+33)-5 (= KA^ > max(-K1ICd+21,18,IMgood+23)).

For SM/DM DSADR develop at different times.  DSADR[25,26] are ready by IMgood+I3205+H40 (= IMgood+18+10 = IMgood+28), DSADR[27] by max(IMgood+I3205+H08,-K1ICd+H04+H04+I3404clock,F9312+I3404data)+H50 (= max(IMgood+18+12,-K1ICd+7+7+13,9+9)+10 = max(IMgood+40,-K1ICd+37,28).  This is fast because the I3404 and F9312 are typical for the Y<0 branch condition.  DSADR[28,31] are good by max(-K1ICd+H04+H04+I3404clock,F9312+I3404data)+H50 (= max(-K1ICd+7+7+17,16+12)+10 = max(-K1ICd+41,38)).  DSADR[32,35] are good by max(-K1ICd+H04+H04+I3404clock,F9312+I3404data)+S02+N28 (= max(-K1ICd+7+7+17,16+12)+5+12 = max(-K1ICd+48,45).

Since DSADR[32,35] are cleverly assigned to chip addresses A0-A3, which have 20 faster readout, the optimal KA^ timing is for DSADR[25,31] ready by KA^+10, DSADR[32,35] ready later, before KAd-7, so:

	KA^ > IMgood+18 for DSADR[25,26]
	KA^ > max(IMgood+30,-K1ICd+27,18) for DSADR[27]
	KA^ > max(-K1ICd+31,28) for DSADR[28,31]
	KAd > max(-K1ICd+55,52) for DSADR[32,35]

Addresses are then valid from max(KA^+24,-K1ICd+67,64) to C+KA^+16.

The above analysis suggests -K1ICd < -3, so that KA^ is constrained by when bus data is good rather than by -K1ICd.

Non-standard usage of KBS on the bipolar cards (an M3026 instead of the usual H04+N28) has been observed to delay both edges of KBS by 10 on the MAP card, so a variation of 8 to 13 is probably about right.  M3026 output goes to 18 places, so it is a little slow.  From the above we have C + KBS^ > KA^+76.

**At the moment, the same address clock is used for MAP and SM.  It may be desirable to retain the old bipolar MAP board after upgrading to new bipolar boards everywhere else (because MAP4_ permits four registers to be written at once on the old boards but only two at once on the new boards).  If so, an earlier address clock could be used for MAP, lessening the read constraint while worsening the write constraint.


SM/DM AND MP WRITES (old PC boards)

3107A storage on bipolar cards is subject to the following write constraints:  The write enable must be 50 wide; addresses and selects must be valid 10 before to 10 after the write enable, and data must be good for 60 before and 10 after the rising edge of write enable.

The write clock is -KW+H04+H00.  The H04+H00 on the MAP card was observed to delay -KWd by 16 and -KW^ by 19.  On an IM board, it was observed delayed by 24.  For analysis, assume maximum clock spread is -KWd+13 to -KW^+24.

*-KWIM is 5 narrower than -KW, and needs to be 50 wide.  Also, various bipolar boards in the SM/DM and MAP slots had write failures at -KW width of 50 cured by making -KW 56 wide.  Hence, -KW should be about 58 wide.

From the read discussion, addresses are valid from KA^+35 to C+KA^+16.  From the fast source discussion, the data is valid from max(KBFd+70,KBF^+46+C)+H08 to C+min(KBFd+35,KBF^+22+C)+H08 or from max(KBFd+82,KBF^+58+C) to C+min(KBFd+41,KBF^+28+C).

Hence:	-KWd+13+C > max(-K1ICd+60,57,KA^+35)+10 (= -KWd+C > max(-K1ICd+57,54,KA^+32));
	-KW^+13+C > max(KBFd+82,KBF^+58+C)+60 (= -KW^+C > max(KBFd+129,KBF^+105+C);
	-KW^+24 < KA^+16-10 (= -KW^ < KA^-18);
	-KW^+24 < min(KBFd+41,KBF^+28+C)-10 (= -KW^ < min(KBFd+7,KBF^-6+C));
	-KW^ - -KWd = 50.  **see comment above


IM READ (old PC boards)

IM direct outputs are good from KIMA^+84 (see above)+15 for load capacity until KIMA^+H00+I3404clock+min(H08+5,15)+C (= KIMA^+5+7+11+C = KIMA^+23+C).

IFCN[xx] signals are most heavily loaded by 12 I3205's (5 pf), 8 3107A outputs (9 pf), 1 S08 (6 pf), 2 N38's (6 pf), 1 8T10 (6 pf), 1 390-ohm pullup (3 pf?), and about 3 feet of wire (45 pf), so total load on these is about 208 pf, 390-ohm pullup.  The spec sheet suggests a delay of 20 in the turn-off time and 7 in the turn-on time for this loading.  The analysis here assumes 15 delay for this.

Other signals potentially troublesome are IBA[xx] and IBT[xx] which are used on both upper and lower backpanels.

KBSI^+M3026+C > KIMA^+99 and KBSId+M3026 < KIMA^+23 (= KBSI^+C > KIMA^+91 and KBSId < KIMA^+10).  -EB data will then be valid from KBSI^+40 until KBSId+36.  Hence, KEBLd+H04 < KBSId+36-I3404hold (= KEBLd < KBSId+21).  Also, KEBLd+H04 > KBSI^+40+I3404setup (= KEBLd > KBSI^+47).

The proper delay of KBSI from KBS and of the delayed KEBL from the regular KEBL will be worked out later.

When EREG is the source, -_EREG must develop early enough to keep KEBL low.  Hence, KD^+H04+I3404clock+H04 < KEBL^-H52-M3026 (= KD^+7+17+10 < KEBL^-15-12 = KD^+61 < KEBL^).


IM WRITE (old PC boards)

On a write, 3107A inputs are good by max(KEBF^+40+C,KEBFd+73)+H08 and remain good until C+KEBFd+35+H08 (= max(KEBF^+52+C,KEBFd+85) to C+KEBFd+41).  Chip selects and addresses are good by KIMA^+42 and remain good until C+KIMA^+16 (analysis = SM/DM write analysis, except card select is ready at H08+H04 rather than at H08 after KIMA^+H00+I3404clock).  The maximum write clock spread is -KWIMd+13 to -KWIM^+24.

Hence:	-KWIMd+13+C > KIMA^+42+10 (= -KWIMd+C > KIMA^+39)
	-KWIM^+13+C > max(KEBF^+52+C,KEBFd+85)+60
		(= -KWIM^+C > max(KEBF^+99+C,KEBFd+132);
	-KWIM^+24 < KIMA^+16-10 (= -KWIM^ < KIMA^-18);
	-KWIM^ - -KWIMd = 50.


SM/DM AND MP READS (new PC boards)

N82S10's have valid direct outputs by max(45 after address good, 30 after chip select good) and the direct outputs turn off by 30 after chip select off.

Chip addresses are ready at KA^+H00+I3404clock (both typical).  Chip enable then passes through H00+H00 or H00.  Both enables and addresses drive 20 chips each with negligible input current and 4 pf typical capacity (about 95 pf).  This means addresses change between KA^+5+7 and KA^+7+13 (= KA^+12 to KA^+20), chip selects between KA^+24 and KA^+36.

Hence, direct outputs are good from KA^+65 to KA^+18(?).

The read clock is KBS+H00+H40, approximately equivalent to the standard H04+N28 usage.  Hence, KBS^+H00+H40+C > KA^+65 (= KBS^+C > KA^+55).

Parity-error signals are valid on BEB from KA^+65+S280+S86+S86+H00 (= KA^+65+21+10+10+7 = KA^+113) until KA^+H04+I3404clock+I3404data+H00+C (= KA^+5+7+7+5+C = C+KA^+24).  They are clocked into LS175's by -KPE^+H04+H40, so -KPE^+5+5+C > KA^+113+LS175setup and -KPE^+7+8 < KA^+24 (= KA^+9+C > -KPE^+C > KA^+123).


SM/DM AND MP WRITES (new PC boards)

For N82S10 writes:  write enable > 35 wide, data good from 40 before until 5 after rising edge of write enable, and chip selects and addresses good from 5 before until 5 after write enable.

From the read discussion, chip addresses and selects are good from KA^+36 to C+KA^+12.  Data is good from max(KBF^+46,KBFd+70)+8T93 to C+min(KBF^+22,KBFd+35)+8T93 = from max(KBF^+56,KBFd+80) to C+min(KBF^+25,KBFd+38).  Parity input is ready by max(KBF^+46,KBFd+70)+S280 (typical) = max(KBF^+60,KBFd+84).  Hence, all data is good from max(KBF^+60,KBFd+84) to C+min(KBF^+25,KBFd+38).

The write enable is -KW+S86+H00 (14 loads), so maximum spread of write enable is -KWd+5+5 to -KW^+10+8 = -KWd+10 to -KW^+18.

Hence:	-KWd+10+C > KA^+27+5 (= -KWd+C > KA^+22);
	-KW^+10+C > max(KBF^+60+C,KBFd+84)+40 (= -KW^+C > max(KBF^+90,KBFd+114));
	-KW^+18 < KA^+12-5 (= -KW^ < KA^-11);
	-KW^+18 < min(KBF^+25+C,KBFd+38)-5 (= -KW^ < min(KBF^+2,KBFd+15);
	-KW^ - -KWd = 35.


IM READ (new PC boards)

IM direct outputs are good from KIMA^+65+(10 for load capacity) to KIMA^+18(?) (see SM/DM analysis above).

IFCN[xx] signals are loaded by 12 I3205's (5 pf), 4 82S10's (7 pf), 1 S00 (6 pf), 2 N38's (6 pf), 1 8T10 (6 pf), 1 390-ohm pullup (3 pf), and 3 feet of wire (45 pf), for a total load of 158 pf, 195 ohms.  The specification isn't clear about the affect of this loading, but assume 10 delay.

C+KBSI^+H00+H40 > KIMA^+75 (= C+KBSI^ > KIMA^+64) and KBSId+H00+H40 < KIMA^+18 (= KBSId < KIMA^+3).  -EB data will then be valid from KBSI^+43 until KBSId+33, so KBSI^+43+I3404setup < KEBLd+H04 < KBSId+33-I3404hold (= KBSI^+50 < KEBLd < KBSId+18).


IM WRITE (new PC boards)

On a write, N82S10 inputs are good from max(KEBF^+40,KEBFd+78)+8T93 to C+KEBFd+35+8T93 (= max(KEBF^+50,KEBFd+88+C) to C+KEBFd+40).  Parity input derived on BEB is good from the previous cycle.

Chip selects and addresses are good from KIMA^+36 to C+KIMA^+12.

Maximum write clock spread is -KWIMd+10 to -KWIM^+18.

Hence:	-KWIMd+10+C > KIMA^+36+5 (= -KWIMd+C > KIMA^+31);
	-KWIM^+10+C > max(KEBF^+50+C,KEBFd+88)+40 (= -KWIM^+C > max(KEBF^+80,KEBFd+118));
	-KWIM^+18 < KIMA^+12-5 (= -KWIM^ < KIMA^-11);
	-KWIM^ - -KWIMd > 35.


INSTRUCTION FETCH AND DECODE

For instruction decoding I3404 write enables are as follows:
	KI+H04 for IM direct outputs, CARRY1, and CJ&SJC;
	KD+H04 for direct outputs through at most one I3205;
	KA+H04 for direct outputs through at most one I3205+2 gates.

Furthermore:
	Destination enables change no earlier than KA^+H04+I3404clock+H04;
	Fast source enables change at KD^+H04+I3404clock+H04;
	Slow source enables change at one of the above.

A fast source enable typically meets KBF+H04 at an N28.  The output of the N28 is the enable for the bus drivers.  Hence, KD^+5+7+5 > KBFd+7 (= KD^ > KBFd-10).  KBF^ cannot occur until the new source is decoded or max(IMgood+I3205+I3404data,KD^+7+17+10) < KBF^+5+C (=KBF^+C > max(IMgood+25, KD^+29)).

KId and KDd can be made late enough to ensure the correct stuff is latched.  However, PSEL and ALUF outputs are assumed valid at KI^+H04+5 elsewhere in the analysis, so IMgood < KI^+10 for these signals which aren't heavily loaded.

I think the longest decoding path for destinations is from -DOCRLFL on DECODE to STOPLOOP on COND to -NEWG.  This path is good at KA^+H04+I3404clock+H50+H08+H00+H00+H52+H53 = KA^+7+17+10+12+10+10+15+11 = KA^+92.  It is needed by -K1IC^+H04+H04-N175setup+C, so -K1IC^+5+5-20+C > KA^+92 (= -K1IC^+C > KA^+102).

F9312 controls on YINT are ready at KA^+H04+I3404clock+F9318datadata (= KA^+7+17+27 = KA^+51) and needed by C-F9312select-Z+F9312data-Z = C-10, so KA^ < C-61.  This isn't as bad as -DOCLRFL.

Slow source enables are needed by KBS^+H04 or on bipolar cards by KBS^.  These constraints are C+KBS^+H04 > KA^+H04+I3404clock+N28 (= C+KBS^ > KA^+31).

None of these is stringent, so latching inputs as late as KAd+H04-I3404setup = KAd-7 is ok.
**If necessary a delayed KA could be used to latch slow sources and destinations, provided the latch clock for -SHUTUPIR were also delayed.

This results in the following constraints:

    OLD PC BOARDS:
	C+KI^+H04 > KIMA^+84-5 (= C+KI^ > KIMA^+74--no capacity correction);
	C+KBF^ > max(KIMA^+84+15+25,KD^+29+C) (= C+KBF^ > max(KIMA^+124,KD^+29+C)--15 capacity cor.
	C+KAd+H04-I3404setup-H21-H21-I3205 > KIMA^+99 (= C+KAd > KIMA^+144--15 capacity correction);
    NEW PC BOARDS:
	C+KI^ > KIMA^+55 (no capacity correction);
	C+KBF^ > max(KIMA^+100,KD^+29+C)--10 capacity cor.
	C+KAd > KIMA^+120 (10 capacity correction).

ALU

Control signals for S181's develop on XACRL at ALUCON = max(IMgood+I3404data,KI^+H04+I3404clock)+H04 (= KI^+5+7+5 to max(IMgood+12,KI^+7+17)+10 = KI^+17 to max(IMgood+22,KI^+34) worst case.  KI^+21 to KI^+31 was observed).

Input data is ready by max(-K1ICEd+M3002+M3002+I3404clock,-KP^+H04+I3404clock,0+F9312+I3404data) (= max(-K1ICd+16+17,-K1ICd+1+7+17,15+12) = max(-K1ICd+33,27)).

Non-arithmetic output is then ready by max(27,KI^+34,IMgood+22,-K1ICd+33)+S181AnyF (= max(57,KI^+64,IMgood+52,-K1ICd+63)).

CARRYIN is ready by max(-K1d+I3404clock,KI^+H04+I3404clock,IMgood+I3205+I3404data)+H52 (= max(-K1d+32,KI^+39,IMgood+45).

Arithmetic output = ALUgood is ready by max(CARRYIN+S182CinCout,max(ALUCON,DATA)+S181inG/Pout+S182G/PinCout)+S182CinCout+S182CinCout+S181CinAnyF = max(CARRYIN+10.5,max(ALUCON,DATA)+15+7)+10.5+10.5+12 = max(CARRYIN+43.5,max(ALUCON,DATA)+55) =  max(IMgood+88.5,-K1ICd+88,82,KI^+89).  Note on the ALUB[0,11] card that carryin propagates through the S182 to the last of the three S181's in the adder, which settles to the result.

ALUZxx outputs are also ready at this time.

Output bad = ALUbad = min(-K1ICd+2+H04+I3404clock,KI^+H04+I3404clock+H04)+S181min = min(-K1ICd+15,KI^+17)+6? = min(-K1ICd+21,KI^+23).

ALU output is needed soon enough to drive the bus, to write LM or RM, prior to -K2 freezing the ALU latch, and early enough for NOT(ALU)Q RCY.  The ALUZxx outputs are needed for the logic on COND.

The bus constraint is  -KALUd+H00+C > ALUgood+I3404data (= -KALUd+C > ALUgood+7).  Also, -KALU+H00 = KBS+H04+N28, so -KALU = KBS+8 approximately.

-K2 constraint is -K2d+H04+H04+H04+C > ALUgood+I3404setup (= -K2d+20+C > ALUgood+12 = -K2d+C > ALUgood-8, where the three H04's are slow due to heavy load).  Also, new P and Q must not propagate through the ALU before it is frozen, so -K2d+26 < ALUbad (= -K2d+34 < ALUbad).

Also, control signals must not change until -K2 has frozen output, so -K2d+26+I3404hold < KI^+17+6? (= -K2d+11 < KI^).

On MISC, -ALUF0 is latched by -K2 for overflow calculation, so KI^+H04+I3404clock-I3404hold > -K2d+H04 (= KI^+5+7-8 > -K2d+7 = KI^ > -K2d+3).

Also on MISC, the slowest path to ALUC1 is -ALU[00]+I3404data+S86+H08+S86 producing ALUC1.  ALUC1 meets -K1IC*+H08+N28 to form the set signal for an N270.  Hence, ALUgood+12+10+12+10 < -K1ICd+6+6+C (= ALUgood < -K1ICd-32+C).  The NOT(ALU)Q RCY constraints are discussed in the next section.

On COND, -K2d+H04+H04+H04+C > ALUgood+H30+I3404setup (= -K2d+5+5+5+C > ALUgood+11+12 = -K2d+C > ALUgood+8) so the ALU=0 branch condition is ready before it is frozen.  Also, -K2^+H04+H04+H04+I3404clock > -K1IC^+H00+H20+I3404hold (= -K2^ > -K1IC^-4) so new ALU output doesn't glitch the branch condition before it is latched.  -K2d+H04+H04+H04+I3404hold < -K1ICd+H04+H20+I3404clock+H04 (= -K2d < -K1ICd-7) for -OLDALU0.

In summary:
	ALUgood = max(IMgood+88.5,-K1ICd+88,82,KI^+89)
	ALUbad = min(-K1ICd+21,KI^+23)
	-KALUd+C > ALUgood+7 for driving bus
	-K2d+C > ALUgood-8 for ALU latch
	-K1ICd+C > ALUgood+32 for ALUC1
	-K2d+C > ALUgood+8 for ALU=0 branch condition
	-K2d+34 < ALUbad to freeze ALU before it changes
	-K2^ > -K1IC^-4 so new ALU doesn't glitch branch condition
	-K1ICd > -K2d+7 for -OLDALU0


P-REGISTER

There is a short path in loading P from the cycled value of Q.  This path requires KPd+H00+I3404hold < -K1ICEd+M3002+M3002+I3404clock+F9312+F9312+F9309 (= KPd+8+8 < -K1ICEd+16+7+6+6+6 = KPd < -K1ICEd+25).

Because Q write enable is about -K1IC+16, compared to about -K1IC+9 for P (to fix the short path), P latch inputs are not needed until -K1ICd+16+5, provided -K1IC^+9 > -K1ICd+21+I3404setup (= -K1IC^ > -K1ICd+24).  Hence, the analysis below computes the timing of the P latch inputs for each of the slow paths (NOT(ALU)Q RCY, LM/RM, multiplexor selects, and masking), then requires these paths be shorter than -K1ICd+21+C.  If -K1IC is wide enough, the paths can be longer at the expense of worsening ALU timing because P ALU inputs will be later than Q.

LM/RM addresses are ready by max(max(KI^+H04+I3404clock+H11+F9309sel-Z,0+F9312+I3404data+F9309data-Z)+I3404data,-K2^+H04+I3404clock) = max(max(KI^+7+17+12+23,16+12+15)+12,-K2^+7+17) = max(KI^+71,55,-K2^+24).  LM/RM enables are ready by max(addressgood+F9309sel+Z-F9309sel-Z,max(0+F9312+I3404data+H21,KI^+H04+I3404clock+H11)+H55+I3404data)+S08 = max(addressgood+32-24,max(16+12+12,KI^+7+17+12)+11+12)+7.5 = max(addressgood+15.5,70.5,KI^+66.5).  Since read timing from select is 18 better than from address, LM/RMgood = max(KI^+71,55,-K2^+24)+3101Adata = max(KI^+106,90,-K2^+59).  Hence, P latch inputs are good by LM/RMgood+F9312data-Z+F9312data-Z+F9309data-Z = LM/RMgood+16+16+15 = max(KI^+153,137,-K2^+106).

The QX inputs are ready well before -PQ[xx].

-PQCTL[1] and -PQCTL[0], controlling the PQ, 0Q, QQ, NOT(ALU)Q multiplexor, are good by KA^+H04+I3404+H40 = KA^+7+17+6 = KA^+30, well before ALU input.  Hence, -PQ[xx] inputs are good by ALUgood+F9309data-Z = ALUgood+15, and P latch inputs by ALUgood+62.

Top F9312 multiplexor controls are ready by PSELgood = max(KI^+H04+I3404clock+H08,-K1ICd+H04+H00+I3404clock,0+F9312+I3404data)+S64+8223+I3404data = max(KI^+7+17+12,-K1ICd+7+7+17,28)+5+50+12 = max(KI^+103,-K1ICd+98,95).  Then P latch input is good by PSELgood+F9312sel-Z+F9312data-Z+F9309data-Z = PSELgood+26+16+15 = PSELgood+57 = max(KI^+160,-K1ICd+155,152).

For masking, DOMASK is good by IMgood+H04+H21 (no problem).

F9309 mask multiplexor selects on XACRL are good by IMgood+S20+S08 (= IMgood+12.5); F9309 inputs by max(KI^+H04+I3404clock,-K1ICd+H04+H04+I3404typclock,0+F9312+I3404typdata) = max(KI^+7+17,-K1ICd+7+7+13,25) = max(KI^+24,-K1ICd+27,25) = 25.

P mask ROM outputs are ready by max(max(25+F9309data+Z,IMgood+12.5+F9309select+Z)+I3404typdata),KA^+H04+I3404typclock)+H04typ+H00typ+8223data (= max(max(25+24,IMgood+12.5+32-C)+9),KA^+7+13)+7+7+50 = max(122,IMgood+117.5-C,KA^+84), and P latch inputs are good by this+F9312enable-Z+F9309data-Z = max(122,IMgood+117.5-C,KA^+84)+23+15 = max(160,IMgood+155.5-C,KA^+122).

In summary, -K1ICd+C > the following:
	ALUgood+41 for NOT(ALU)Q RCY
	max(KI^+132,116,-K2^+85) for LM/RM
	max(KI^+139,131,-K1ICd+134) for multiplexor controls
	max(139,IMgood+137-C,KA^+101) for masking

KI+H04 latches 6 PSEL signals addressing the ROM.  Y also figures into the PSEL determination.  One worry is that new PSEL will slip through too soon.  The final F9309 selects are held up by -K2, so they aren't a problem.  Hence, the constraint on these is min(KI^+H04+I3404clock+H04,-K1ICd+H04+H04+I3404clock)+S64+8223+H04+F9312sel+F9309data > KPd+H04+I3404hold (= min(KI^+5+7+5,-K1ICd+5+5+7)+3+15?+5+8?+6? > -K1IC^+1+10+8 = min(KI^,-K1ICd)+35 > -K1IC^).

Notes:
(1)  Use of S04's rather than I3404's to receive the top P-multiplexor controls would save 7 on that path.
(2)  Replacing the 8223's by 82S23's would save 10 in the mask path.
(3)  Typical F9309's and I3404's are used in the mask path, so the timing is actually about 10 better than above.
(4)  Using a narrow, late -K1IC for Q (say 0 to 20 rather than -7 to 20) allows KP to be a normal -K1IC rather than an early one.  This saves 8 in the P timing while slowing ALU timing by about 6.


Q REGISTER

There are no problems with Q timing except those arising from the fact that -K1ICE is delayed a long time.  Hence, to ensure RM/LM data good long enough, -K2^+H04+I3404clock+3101A+F9312 > -K1ICE^+M3003+M3003+I3404hold (= -K2^+5+7+6+6 > -K1ICE^+21+8 = -K2^ > -K1ICE^+6).