Maxc OperationsInterpreting Checker Failures3311. INTERPRETING CHECKER FAILURESThe microcode Checker is normally run whenever Tenex is started or restarted, and may be runmanually by issuing the Midas command "25;G". Checker failures are characterized by:a)IMA=20b)STK 0 = RETN (type "RETN=" to verify this)c)a value in LM 10 between 0 and 77777.To interpret a Checker failure, the following guidelines are offered:a)If LM 10 contains 0, all SM, DM, DM1, DM2, and IM registers containing constantswere verified to be correct, but some LM or RM constant or other processor operationfailed. See the microinstruction at [STK 0]-1 in the Checker listing to determine what'swrong.b)If LM 10 does not contain 0, it contains the logical "or" of all addresses containingincorrect values, where00000-07777Instruction memory (IM) bits 0-3510000-17777Instruction memory (IM) bits 36-7120000-23777Dispatch memory (DM) 0-377724000-24777Scratch memory (SM) 0-777Since these memories are composed of chips which span 400 or 2000 (octal) bits andsince the normal failure mode is complete chip failure, it will seldom be true that thenumber in LM 10 is the address of a single failure. For total chip failures, the logical"or" of the addresses will wind up in LM 10. Note that on the old bipolar boards, chipsare interleaved so that a chip hits every fourth address. The value in register LPGRT3is the complement of the wrong bits in the word if there was only a single error.c)On Maxc2, one can obtain additional information by invoking "LMPE-Scan" to find thebipolar memory locations containing parity errors, and by invoking "Compare"1 tocompare the current memory contents with the file from which the control memory wasloaded. (Note that it is normal for "Compare" to find one error at location IODEND.)d)Run the DGIMH and DGIML micro-diagnostics for further error information.------------------------------1"Compare" (Ref. Section 2, par. C.3.) produces a list of errors on file Midas.Error. From the Alto executive issue thecommand "Type Midas.Errors". The number associated with each error is a 36 bit word numbered from left to right bit0 through bit 35. These bit numbers correspond to the bit numbers identified in the bipolar memory card chip maps(Figures 1, 2 & 3). fpi3gq XFpA_r" \1sG ZfUCVCSX*CP% LECI-KGbDE5$CC@[U><8 "X!:n ""8 "6 "452W0C/!C-V0'+QC(;&OL&t&Os$O"UCHH @t &Z [3A m  =QN TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMAN  TIMESROMANj/ }!MaxcOps11.BravoRWeaverJuly 16, 1981 10:51 AM