// AltIOMaxc2.decl -- Maxc2 hardware-defined parameters for AltIO


manifest
[
//SMI input addresses
smiRUN = #200	//processor run status
smiB0 = #203	//processor bus
smiB1 = #202
smiB2 = #201
smiJKERRS = #43	//memory errors for quadrants J and K
smiLMERRS = #44	//memory errors for quadrants L and M
smiPPSTAT = #100  //port and processor power status
smiCABST = #20  //memory power status (smiCABST + 2*cabinet)

//SMI output addresses
smiBR0 = #213	//processor bus
smiBR1 = #212
smiBR2 = #211
smiPIR0 = #217
smiPIR1 = #216	//pseudo-instruction register
smiPIR2 = #215
smiPIR3 = #214
smiCR = #210	//control register
smiPLMR = #40	//physical/logical memory module register
smiCONFR = #41	//memory configuration register
smiRESR = #42	//memory error reset register
]


//layout of selected registers.
//note that output registers consisting entirely of single
//bits are defined by mask bits rather than structures
//since it's easier to construct them in BCPL this way.

structure RUN:	//processor run status
   [
   blank bit 8
   running bit		//processor is running
   notBreakpoint bit	//not at micro breakpoint
   localPE bit		//local memory parity error
   mainPE bit		//main memory data bus parity error
   ]

structure QErr^0,3 byte	//memory error register (2 words)
manifest		//layout assuming byte right-justified
   [
   qeTimeout = #40
   qeDIP = #20
   qeAPE = #10
   qePBF = #4
   qeDE = #2
   qeSE = #1
   ]

manifest	//processor control register
[
crEIC = #100000	//enable instruction controlled changes
crEB = #40000	//enable changes to branch conditions
crEIMA = #20000	//enable changes to IMA
crENPC = #10000	//enable changes to NPC
crNOTSS = #4000	//don't single step
crSetRun = #2000 //set the run flipflop
crReset = #1000	//reset processor-memory interface
crEPIR = #400	//execute instructions from PIR rather than IM
crRegToB = #200	//put BR register on processor bus
crIntOn = #100	//enable micro-interrupts
crStrobe = #40	//generate interprocessor signal

//normal value sent to CR (e.g., when setting Strobe)
crNormal = crEIC+crEB+crEIMA+crENPC+crNOTSS+crIntOn
]

structure PLMR:	//physical/logical module register
   [
   blank bit 7
   disableCorrection bit
   logicalModule bit 3
   physicalModule bit 3
   quadrant bit 2
   ]

structure CONFR:  //configuration register
   [
   blank bit 4
   eFER bit	//enable reporting of fatal errors
   configuration bit 3  //address/quadrant map
   jSEF bit	//quadrant J single errors fatal
   jPBFF bit	//quadrant J parity bit failures fatal
   kSEF bit
   kPBFF bit
   lSEF bit
   lPBFF bit
   mSEF bit
   mPBFF bit
   ]
manifest allSEF = #252
manifest allPBFF = #125
manifest enableFER = #4000

structure RESR:  //error reset register (all bits complemented)
   [
   blank bit 8
   jResetErrors bit  //reset errors in quadrant J
   jResetQuadrant bit  //completely reset quadrant J
   kResetErrors bit
   kResetQuadrant bit
   lResetErrors bit
   lResetQuadrant bit
   mResetErrors bit
   mResetQuadrant bit
   ]
manifest allResetErrors = #125
manifest allResetQuadrant = #252

structure SMIErr:  //SMI error register
   [
   blank bit 11
   comb bit	//communication strobe B (unused)
   coma bit	//communication strobe A
   nfer bit	//non-fatal error
   fer bit	//fatal error
   blank bit
   ]
manifest smiErrorMask = #12  //bits that we care about (coma, fer)