Y REGISTER
Second-rank I3404 output is good by -K2↑+H04+I3404clock = -K2↑+7+17 = -K2↑+24. Control signals for H87's, H183's, and N283's are ready by KA↑+H04+I3404clock = KA↑+7+17 = KA↑+24.
Hence input to the Y I3404's is good by max(-K2↑+24+H87data,KA↑+24+H87select)+N283inCout+N283CinCout+H183+F9312 (= max(-K2↑+24+20,KA↑+24+25)+16+16+18+16 = max(-K2↑+110,KA↑+115). It is needed by -K1ICd+H04+H04+5 so -K1ICd+C > max(-K2↑+93,KA↑+98).
RUN AND NOEX SIGNALS
KDR clocks assorted N175's on PMAINT and the S112 for RUN. N175's require clock width of 20, suggesting KDR be 24 wide. KDRd should be set so that FDORUN3↑ < KSTK↑ to enable KSTK↑, FDORUNd < KSTK↑-4 to disable KSTK (**Why does KSTK have to be enabled by FDORUN?), and FDORUN3↑d < KAd+H04-I3404setup (= FDORUN3↑d < KAd-7) for the DORUN latch. DORUN enables -SHUTUPIR and various late clocks, the earliest of which are -KW and -K3IC.
FDORUN1/2/3 also enable KIMA, so FDORUN↑ < KIMA↑ and FODRUNd < KIMA↑-4.
KDRd+H08-S20-H53-S112setup+C > IBREAKgood (= KDRd+6-5-10-3+C > IBREAKgood = KDRd+C > IBREAKgood+12) for the breakpoint bit to enable FDORUN.
IMgood+I3205+S10+H53 < min(KSTK↑-4,KAd-7,KIMA↑-4)+C for the various memory function, destination, and source decoding paths which enable FDORUN (= IMgood+5+10 < min(KSTK↑-4,KAd-7)+C = IMgood < min(KSTK↑-19,KAd-22,KIMA↑-19)+C).
PIR is shutoff on an IM read from the Alto by KA↑+H04+I3404clock+N28+H04+H20+H40+8T10disable = KA↑+5+7+6+5+5+5+5 (min) to KA↑+7+17+11+10+10+10+30 = KA↑+38 (min) to KA↑+95 (max). Direct outputs are needed until KAd+H04+I3404hold-I3205 = KAd+10 so that destinations can be safely latched on an IM read/write from the Alto. There is danger that it will turn off too slowly because IM direct outputs will be good by KIMA↑+65 on the new PC boards or KIMA↑+84 on the old, and also it may turn off too quickly.
However, observed timing is -SHUTUPIR↑ = KA↑+25 and -SHUTUPIRd = KA↑+33. Hence, PIR is shutoff by KA↑+25+H40+8T10disable, and on by KA↑+33+H40+8T10enable (= off between KA↑+37 and KA↑+65, on between KA↑+45 and KA↑+73). This means that KAd < KA↑+27.
-NOEX enables -DOIBREAK, KD, and KA on MISC, forces KEBF to stay high, and produces -NOEXA/B; on DECODE it enables -LOADPC, on YINT it enables -IR, and on CONTROL it forces no-branch on interrupts. For these uses it must occur after -KNPCSEL↑+I3404hold-S10-H40, before KDRd+H08-S112setup-S20-H53-S08 for -DOIBREAK and must last until after that time in the next cycle.
-NOEX develops at -K3+I3404clock. So, -KNPCSEL↑+8-3-5 < -K3d+7 (= -KNPCSEL↑ < -K3d+7). -NOEX is developed from -IMREF, so KA↑+H04+I3404clock+N28+H04+M3002 < -K3d+5 (= KA↑+7+17+12+10+12 < -K3d+5 = KA↑+53 < -K3d). This develops -NOEX by -K3d+I3404clock (= -K3d+17). For -DOIBREAK, -K3d+17 < KDRd+6-3-5-11-7 (= -K3d+37 < KDRd).
For -IR, -K3↑+H08+H40+H04+I3205+M3026+H53+H51 < KIMA↑+H00+5 (= -K3↑+12+10+10+13+12+11+14 < KIMA↑+10 = -K3↑+74 < KIMA↑).
RMWIP↑ occurs at KA↑+H04+I3404clock+M3003+S02+N28 at the onset of RMW and RMWIPd at KA↑+H04+I3404clock+H08+N28 in the cycle of the WRESTART. Hence, KA↑+7+17+12+5+12 < -K3↑-I3404setup+C develops RMWIP by -K3↑ (= KA↑+65 < -K3↑+C). For -IR, this means -K3↑+H40+H04+I3205+M3026+H53+H51 < KIMA↑+H00+5 (= -K3↑+10+10+18+12+11+13 < KIMA↑+5+5 = -K3↑+64 < KIMA↑).
-NOEXA/B occur for one cycle at -K1↑+H04+H04+H00+H08+H108clock+H00 or between -K1↑+5+5+5+6+5+5 and -K1↑+10+10+7+12+20+10 = -K1↑+31 to -K1↑+69. -NOEXBd was observed at -K1↑+33, -NOEXB↑ at -K1↑+38.
-NOEXA must remain high for (delayed) KEBL and be low for -K3IC, -KW, -KWIM, and -K1IC. Hence, KEBLd-H52-M3026-H08 < -NOEXAd (= KEBLd-6-6-6 < -K1↑+31 = KEBLd < -K1↑+49). Also, -NOEXA↑d < min(-KWd-10,-K3ICd-10) (= -K1↑+79 < min(-KWd,-K3ICd).
**Make sure -NOEXA↑d occurs as soon after -K1↑+43 (= earliest for KEBL) as possible.
CONTROL TIMING
IMA addresses must be good from KIMAd+H00-S174setup to KIMAd+H00+I3404hold. KIMA↑+H00 should occur 5 before the slowest IMA signal is good, so IMA should be good from KIMA↑+10 to KIMAd+15.
Various branch conditions are ready as follows:
ALU=0 by < 10
ALU<0 by < 10
ALU<=0 by < 10
ALU8=0 by < 10
X<0 by max(-K1ICd+H04+H04+I3404typclock,F9312typ+I3404typdata)
= max(-K1ICd+7+7+13,11+9) = max(-K1ICd+27,20)
Y<0 by max(-K1ICd+27,20)
G=0, etc. by -K1ICd+H04+H04+I3404clock = -K1ICd+27
Q odd by max(-K1ICd+27,20)
B<0 by H50 = 10;
Hence, slowest branch conditions are ready by max(-K1ICd+27,20), suggesting -K1ICd = -7. -K1ICd should be as early as this provided it does not constrain -K2 unfavorably or provoke a short path.
S151 selects are ready by IMgood and enables by IMgood+H04, so -DOBR0 is good by max(IMgood+S151sel-Z,IMgood+H04+S151en-Z,max(-K1ICd+27,20)+S151data-Z) = max(IMgood+max(15,13+10),-K1ICd+34,27) = max(IMgood+23,-K1ICd+34,27).
Hence, IMA[xx] on CONTROL are good by max(-K1ICd+34,27)+S11+S158data+H51 = max(IMgood+50,-K1ICd+61,54). This allows 14 for the H51's which are loaded by an S175 and 16 I3404 inputs. Therefore, KIMA↑+H00 > max(-K1ICd+61,54)-5 (= KIMA↑ > max(-K1ICd+51,44)). Also IMgood = KIMA↑+84 (old boards) or KIMA↑+65 (new boards), allowing no capacity correction since the IFCN2 signals aren't very heavily loaded. So KIMA↑+H00+C > KIMA↑+84+50 (= C > 129 on the old boards or C > 110 on the new boards).
Since KIMA↑ timing is controlled by when NOBRA and NOBRB can be developed, and since the slowest signal latched by -KNPCSEL is at NOBRA+S11, we want KIMA+H00-H51 = -KNPCSEL-S11 or KIMA = -KNPCSEL-6-5+7 = -KNPCSEL-4.
Similarly, NOBRA is the slowest input to mode control latches, so KSTK > KIMA-H51 = KIMA-10.
After a CALL or RETURN, new STK data is ready at -K3IC↑+N28+N28+N194delay = -K3IC↑+9+9+26 = -K3IC↑+44. Hence, KIMA↑+H00+5 > -K3IC↑+44+H53+H51 or KIMA↑+5+5 > -K3IC↑+44+11+14 or KIMA↑ > -K3IC↑+59.
N194 mode controls must be stable 30 before clock↑ and while the clock is low, so min(-K3IC↑-30,-K3ICd)+N28+N28+C > KSTK↑+H00+I3404clock+H51, (= min(-K3IC↑-30,-K3ICd)+6+6+C > KSTK↑+7+17+10 = -K3ICd+C > KSTK↑+22 and -K3IC↑+C > KSTK↑+52). -K3IC > 20 wide for N194's.
-IR on YINT must not be affected by PREIRET or IRET until the next cycle, so KA↑+H04+I3404clock+N28+H08+M3003 > KA↑+H04+H00+I3404hold (= KA↑+5+7+6+6+6 > KA↑+7+10+8 which is true), and KAd+H04+H08+H00+I3404clock+H20+H04+S11 > -KNPCSEL↑+I3404hold (= KAd+5+6+5+7+5+5+3 > -KNPCSEL↑+8 = KAd+28 > -KNPCSEL↑)
Interrupt requests are latched by -K1IC+H04+H04 and the ARM register is latched by -K1IC+M3003 on YINT, so XIR is indeterminate from -K1ICd+M3002+H00+F9318datatogroupd+H00 to -K1IC↑+H04+H04+H00+F9318datatogroupd+H00 (= -K1ICd+6+5+12+5 to -K1IC↑+7+7+10+23+10 = -K1ICd+28 to -K1IC↑+57). The IA[xx] signals are unstable for an additional F9318enabletodata↑ = 15. The requests are latched by -K3+M3003, so -K3↑+M3003-I3404setup+C > -K1IC↑+72 (= -K3↑+C > -K1IC↑+78). The INTIR signal then develops at max(-K3d+M3003+I3404clock, -K1IC↑+69+I3404data) (= between -K3d+6+7 and max(-K3d+9+17,-K1IC↑+57+12) = between -K3d+13 and max(-K3d+26,-K1IC↑+69)).
Following PREIRET, -IR is latched by KIMA in the next cycle. Hence, max(KA↑+H04+I3404clock+N28+H08+M3003+I3404data,KAd+H08+I3404clock,-K3d+26+C,-K1IC↑+69)+H20+H04+I3205+H40+H53+H51 < KIMA↑+H00+5+C (= max(KA↑+9+17+12+12+12+12,KAd+9+17,-K3d+26+C,-K1IC↑+69)+10+10+18+10+11+14 < KIMA↑+5+5+C = max(KA↑+74,KAd+26,-K3d+26+C,-K1IC↑+69)+63 < KIMA↑+C = KA↑+137 < KIMA↑+C, -K3d+89 < KIMA↑, and -K1IC↑+132 < KIMA↑+C).
The IA[xx] signals go through less logic on CONTROL than does -IR, so their constraint isn't as significant.
-INTDONE↑ must occur soon enough to enable the last 18 of -KIA and -INTDONEd soon enough to disable all of -KIA, so KA↑+H04+I3404clock+N28+H08+M3003 < -K3d+C (= KA↑+9+17+12+12+9 < -K3d+C = KA↑+59 < -K3d+C). The observed timing is -INTDONE↑ = KA↑+28 and -INTDONEd = KA↑+22, so KA↑+48 < -K3d+C and KA↑+54 < -K3↑+C-18 (= KA↑+72 < -K3↑+C).
DOINT must occur soon enough to disable -KIA, so -KNPCSELd+I3404clock+M3003 < -K3d+M3003+C (= -KNPCSELd+17+4 < -K3d+C = -KNPCSELd+21 < -K3d+C). DOINT must last long enough to be latched, so -K1IC↑+H04+H00+I3404hold < -KNPCSELd+I3404clock (= -K1IC↑+7+7+8 < -KNPCSELd+7 = -K1IC↑ < -KNPCSELd-15).
INT and INT* must develop before the latches clocked by -K2 get bad data at the end of the interrupt instruction, so -K3d+I3404clock+I3404hold+H08 < -K2↑+H04+I3404clock (= -K3d+17+8+12 < -K2↑+5+7 = -K3d < -K2↑-25).
NPC latches get clocked by KNPC except when an interrupt instruction is fetched and the instruction being executed is not branching. The value loaded into the 8T10 will be either the STK output from the previous instruction (ready in plenty of time) or the IBA signal from the current instruction (also ready in plenty of time).
The enable/disable for the S258's on CONTROL is ready by KBST↑+H04+I3404clock+H04 and for the 8T10's by KBST↑+H04+I3404clock, so these are enabled/disabled by KBST↑+7+17+max(10+21,30) (= KBST↑+55).
The -LB output of the S258's is ready by S04+I3404data+S258data = 23, IMA+1 by KIMAd+H00+S175delay+N283CinCout+N283inCout+N283Cindata+S258data (= KIMAd+7+17+16+16+21+6 = KIMAd+83).
8T10 outputs are ready by KBSTd+H04+8T10clock (= KBSTd+7+25 = KBSTd+32). To ensure that 8T10 inputs are good, KBSTd+H04-8T10setup > max(KBST↑+H04+I3404clock,-KNPCSELd+I3404clock+I3404data)+S157select (= KBSTd-5 > KBST↑+17+15 and KBSTd+5-5 > -KNPCSELd+17+12+15 = KBSTd > KBST↑+37 and KBSTd > -KNPCSELd+44).
8T10/S258 outputs are needed by KNPCd+H00-I3404setup, so KNPCd+5-12 > max(KBST↑+55,KBSTd+32,KIMAd+83-C,23) (= KNPCd > KBSTd+39, KNPCd+C > KIMAd+90, and KNPCd > 30).
Since NPC is a fast source, it should be loaded as early as possible, but not so early that the bus is glitched, so KBFd+H04 < KNPC↑+H00+I3404clock+I3404data (= KBFd+7 < KNPC↑+5+7+7 = KBFd < KNPC↑+12).
Then KBF↑+H04+N28 > max(KNPC↑+H00+I3404clock,KBSTd+32+I3404data,KIMAd+83-C+I3404data,23+I3404data)+I3404data (= KBF↑+5+6 > max(KNPC↑+7+17,KBSTd+32+12,KIMAd+83-C+12,23+12)+12 = KBF↑ > max(KNPC↑+25,KBSTd+45,KIMAd+96-C,36)).
KBSTd must occur after IMA are latched, so KIMAd+H00+I3404hold < KBST↑+H04+I3404clock+S258enable+H53+H51 (= KIMAd+7+8 < KBST↑+5+7+5+6+6 = KIMAd < KBST↑+14).
MEMORY REFERENCES
Discussion below is for PMEMI, identical to KMEMI.
MAR data are ready by -K1IC*↑+H04+H00+S174delay (= -K1IC↑+5+5+6 to -K1IC↑+7+7+17 = -K1IC↑+16 to -K1IC↑+31). Parity is ready by F9348+S280 after this (= -K1IC↑+31+48+21 = -K1IC↑+100). RQ occurs at -K1↑+H04+H08+H108clock (= -K1↑+17 to -K1↑+35). RQ enables the address 8T26A bus. RQ and parity N38's always drive the memory bus. Memory timing must tolerate the delay from RQ to MAR ok and to parity ok.
FETCH and STORE occur at -K1IC↑+H04+H00+H74delay↑ (= -K1IC↑+5+5+5 to -K1IC↑+7+10+15 = -K1IC↑+15 to -K1IC↑+32). The memory bus drivers for these are also enabled by RQ.
MDR data are ready by -K1↑+H04+H00+S174delay (= -K1↑+31). MDR parity for the memory is then ready by -K1↑+100 (same as MAR). PARS occurs for one cycle, lasting until -K1↑+H04+H08+H08+H108delayd+C (= -K1↑+5+6+6+5+C to -K1↑+7+8+8+15+C = -K1↑+22+C to -K1↑+38+C). Hence, inputs to the -MEMPE flipflop on MISC are valid from -K1↑+100+H51+H04 until -K1↑+22+H51+C (= -K1↑+120 until -K1↑+27+C).
-MEMPE is ready by -K1↑+31+F9348PO+S280+S86+H51+H04 and is needed by -K1↑+H04+H04+H00+H08-H108setup+C, so -K1↑+31+48+21+10+10+10 < -K1↑+5+5+6+5-13+C (= C > 122).
DISK CONTROL
KI↑ should occur early enough for bus data ready in case KRDATA occurs, and KId as soon as KRDATA is decoded. Hence, KId > KD↑+H04+I3404clock (= KId > KD↑+7+17 = KId > KD↑+24). Also, KI↑+S32+S157sel+3101Adata+S157data < KEBF↑+M3002+M3002 (= KI↑+7+15+35+7.5 < KEBF↑+6+6 = KI↑+52.5 < KEBF↑).
Multiplexors selected by KRDATA, -KDKU, and -KDKS must have stable output before KEBF↑, so KEBF↑+M3002+M3002 > KD↑+H04+I3404clock+S157sel (= KEBF↑+6+6 > KD↑+7+17+15 = KEBF↑ > KD↑+27).
3101A addresses must be good while -K3IC is low, so -K3IC↑+M3002+H00 < KI↑+S32+S157sel (= -K3IC↑+9+7 < KI↑+3+4 = -K3IC↑+9 < KI↑). -K3ICd+C+M3002+H00 > KId+S32+S157sel (= -K3ICd+C+6+5 > KId+7+15 = -K3ICd+C > KId+11).
KBUF1 and -K3IC must be 25 wide.
SUMMARY OF CLOCK CONSTRAINTS
1. -K1IC↑ > 20 P, STACK
-K1IC↑ > 21 NEWG
-K1IC↑ > 18 X, Y, AC, MDR
2. -B data from fast source is good by max(KBF↑+46,KBFd+70) and remains good until min(KBFd+35,KBF↑+22).
3. **Need E-bus observations for source = BEB, COMCON, IM
4. KBS↑ < -46
KBSd > -K1IC↑-10 keep data good until safely latched
-K1ICd > -K2d+4 P old value frozen
KBF↑+C > -K2↑+13 old data not glitch bus for X, Y, AC, P, Q
KBF↑+C > -K1ICd+34 old Q not glitch bus
KBFd < -K2↑+3 new data not glitch bus
-K1IC↑ < -K2↑+12 no short path for X, AC
-K1IC↑ < -K2↑-3 no Q short path
KBF↑+C > -K1IC↑+6 S174 sources
min(KBFd+18,KBF↑+5+C) > -K1IC↑ slowest destinations latched
KBF↑+C > max(KNPC↑+25,KBSTd+45,KIMAd+96-C,36) NPC ready for bus read.
KBFd < KNPC↑+12 new NPC not glitch bus
5. KBS↑ > max(KBFd+54-C,KBF↑+31) -B valid before driving -EB
KBS↑ < KEBL↑-30 -EB data good when latched
KEBL↑ = KBS↑+30 good seeting for KEBL↑
KBSd > KEBLd-30 -EB data still good when latched
KBS↑ > max(KBFd+70-C,KBF↑+32) -EB valid before driving -B
KBSd < KA↑+5 -E←B changing while bus connections disabled
6. KBF↑+C > KD↑+29 new source selected before KBF↑
KD↑ > KBFd-10 keep old source selected until KBF shuts off
7. KA↑ > max(-K1ICd+21,18,IMgood+23) MP addresses
KA↑ > IMgood+18 DSADR[25,26]
KA↑ > max(IMgood+30,-K1ICd+27,18) DSADR[27]
KA↑ > max(-K1ICd+31,28) DSADR[28,31]
KAd > max(-K1ICd+55,52) DSADR[32,35]
OLD PC BOARDS:
KAd > KA↑+28 for heavily loaded latch outputs
KBS↑+C > KA↑+76 direct outputs of SM/DM/MP valid before KBS
NEW PC BOARDS:
KAd > KA↑+24 moderately loaded latch outputs
KBS↑+C > KA↑+55 direct outputs ready before clock
-KPE↑+C > KA↑+123 parity good soon enough
-KPE↑ < KA↑+9 parity good long enough
8. OLD PC BOARDS
-KWd+C > KA↑+32 chip selects good 10 before write enable
-KW↑+C > max(KBFd+129,KBF↑+105+C) 60 data setup
-KW↑ < KA↑-18 address good 10 after write clock
-KW↑ < min(KBF↑-6+C,KBFd+7) data good 10 after write clock
-KW↑ - -KWd = 56 clock width
NEW PC BOARDS
-KWd+C > KA↑+22 address good 5 before write enable
-KW↑+C > max(KBFd+114,KBF↑+90+C) 40 data setup
-KW↑ < KA↑-11 address good 5 after write enable
-KW↑ < min(KBF↑+2+C,KBFd+15) data good 5 after write enable
-KW↑ - -KWd = 35.
9. KD↑+61 < KEBL↑+C -←EREG keeping KEBL low
OLD PC BOARDS:
KBSI↑+C > KIMA↑+91 direct IM outputs ready for bus clock
KEBLd > KBSI↑+47 for EREG
KEBLd < KBSId+21
NEW PC BOARDS:
KBSI↑+C > KIMA↑+65
KEBLd > KBSI↑+48
KEBLd < KBSId+18
10. OLD PC BOARDS
-KWIMd+C > KIMA↑+39 chip selects stable 10 before write clock
-KWIM↑+C > max(KBF↑+99+C,KBFd+132+C) 60 data setup
-KWIM↑ < KIMA↑-18 address good 10 after write clock
-KWIM↑ - -KWIMd = 50
NEW PC BOARDS
-KWIMd+C > KIMA↑+22 chip selects stable 5 before write enable
-KWIM↑+C > max(KBF↑+80,KBFd+118) 40 data setup
-KWIM↑ < KIMA↑-11 address good 5 after rising edge of write enable
-KWIM↑ - -KWIMd = 35
11. KIMA↑ > max(-K1ICd+51,44) NOBRA from branch condition
KSTK > KIMA-10 equal constraint imposed by NOBRA
-KNPCSEL = KIMA+4 equal constraint imposed by NOBRA
KI↑+34 < KIMA↑ IBA ready for branch
-K3d < -K2↑-25 for INT and INT*
-K3↑+C > -K1IC↑+78 IA[xx] latched for int. request
KAd+28 > -KNPCSEL↑ PREIRET and IRET won't glitch -IR
KA↑+137 < KIMA↑+C IMA for interrupt ready after IRET/PREIRET
-K3d+89 < KIMA↑ -IR good after int. request
-K3↑ > -K3d+20 write enable wide enough for I3404's
-K1IC↑+132 < KIMA↑+C IMA good after int. request
KBST↑+37 < KBSTd S157 outputs ready for 8T10 clock on CONTROL
KBST↑+14+C > KIMAd IMA stuff latched before it changes
KBSTd+C > -KNPCSELd+22 -KNPCSEL latch outputs ready for KBST latches
KA↑+62 < -K3d+C -INTDONE to enable -KIA (observed KA↑+48 < -K3d+C)
-KNPCSELd+21 < -K3d+C DOINT disabling -KIA
-K1IC↑ < -KNPCSELd-15 DOINT latched
KNPCd > KBSTd+39 8T10 outputs ready on CONTROL
KNPCd+C > KIMAd+90 IMA+1 S258 outputs ready on CONTROL
KNPCd > 30 -LB outputs ready on control
KIMA↑ > -K3IC↑+59 STK address ready in cycle after CALL or RETURN
-K3ICd+C > KSTK↑+22 stable N194 mode controls when -K3IC is low
-K3IC↑+C > KSTK↑+52 30 setup of mode controls for N194's
-K3IC↑+C > -K3ICd+20 clock width for N194's on STACK
Constraints on -K3, -K3IC, and KBST are clearer as follows:
KA↑+151 < -K3d+89+C < KIMA↑+C
-K1IC↑+137 < -K3↑+59+C < KIMA↑+C
KSTK↑+111 < -K3IC↑+59+C < KIMA↑+C
KSTK↑+22 < -K3ICd+C
KIMAd+63 < KBST↑+76+C < KBSTd+39+C < KNPCd+C
12. KAd < KIMA↑+25 destinations latched before new IM data appears
OLD PC BOARDS:
C+KI↑ > KIMA↑+74 latching direct outputs of IM
2C+KBF↑ > max(KIMA↑+124,KD↑+29+C) latching slowest fast source decode
C+KAd > KIMA↑+144 latching slowest destination decode
C+KDRd > KIMA↑+96 IBREAK ready for RUN flipflop
C+min(KSTK↑,KAd-3) > KIMA↑+118 function decode to FDORUN
C > 129 IFCN2 on CONTROL
NEW PC BOARDS:
C+KI↑ > KIMA↑+55 latching IM direct outputs
2C+KBF↑ > max(KIMA↑+100,KD↑+29+C) latching slowest fast source decode
C+KAd > KIMA↑+120 latching slowest destination decode
C+KDRd > KIMA↑+77 IBREAK ready for RUN flipflop
C+min(KSTK↑,KAd-3) > KIMA↑+94 function decode to FDORUN
C > 110 IFCN2 on CONTROL
13. KA↑+65 < -K3↑+C RMWIPd enabling -IR
-K3↑+64 < KIMA↑ for RMWIP to IMA path
-K3d+37 < KDRd -NOEX to enable/disable -DOIBREAK
-KNPCSEL↑ < -K3d+2 -NOEX not to affect WANTKNPC
KA↑+53 < -K3d -NOEX latch input ready
KAd < KA↑+27 SHUTUPIR after destinations latched
** -K1↑+49 > KEBLd -NOEXA after latching IM in EREG
** -K1↑+79 < min(-KWd,-K3ICd)+C -NOEXA before late clocks
14. KI↑-11 > -K2d ALU controls good long enough
KI↑ > -K2d+3 latching -ALUF0 on MISC
-K2d < -K1ICd-13 new P doesn't clobber ALU before frozen
-K2↑ > -K1IC↑-4 ALU=0 branch condition
-K2d < -K1ICd-7 -OLDALU0
-KALU = KBS+8 approximately
-KALUd+C > ALUgood+7 driving bus
-K2d+C > ALUgood-8 latching ALU
-K1ICd+C > ALUgood+32 ALUC1
-K2d+C > ALUgood+8 ALU=0 branch condition
OLD BIPOLAR BOARDS
ALUgood = max(KIMA↑+187.5-C,-K1ICd+88,82,KI↑+89)
NEW BIPOLAR BOARDS
ALUgood = max(KIMA↑+163.5-C,-K1ICd+88,82,KI↑+89)
15. min(KI↑,-K1ICd)+35 < -K1IC↑ P-multiplexor selects good long enough
KPd < -K1ICEd+25 P←PQ RCY short path
C > 134 multiplexor controls
-K1ICd+C > ALUgood+41 NOT(ALU)Q RCY
-K1ICd+C > max(KI↑+132,116,-K2↑+85) LM/RM
-K1ICd+C > max(KI↑+139,131) multiplexor controls
-K1ICd+C > max(139,KA↑+101) masking
OLD BIPOLAR BOARDS
-K1ICd+2C > KIMA↑+236 masking
NEW BIPLAR BOARDS
-K1ICd+2C > KIMA↑+212 masking
16. -K2↑ > -K1ICE↑+6 LM/RM good for Q
17. -K1IC↑ < KA↑-8 new Q latched before select changes
18. -K1ICd+C > max(-K2↑+93,KA↑+98) Y incrementer
19. C > 122 MDR/KMDR parity error stuff
20. KId > KD↑+24 -KRDATA good before buffer selects change
KEBF↑ > max(KD↑+27,KI↑+52.5) data ready before bus clock
KA↑+32 > KBUF1d > max(KEBL↑+54,KBS↑+82) data and CE's good for buffer 1 write
KBUF1d > KBUF1↑+25 clock wide enough
-K3IC↑+7 < KI↑ address good during buffer 2 write
-K3ICd+C > KId+12 addess good during buffer 2 write
-K3IC↑ > -K3ICd+25 clock wide enough
CLOCK SETTINGS
To illustrate where the machine is slowed, the following are clock settings consistent with previous analysis. 4 margin is allowed on each side of the bus timing.
OLD PC BOARDS MISC NEW PC BOARDS
-K1IC -7 +20 E51 -7 +20
-K2 -25 +26 E66 -22 +19
-K3 -47 -20 E47 -48 -23
KBF -95,39 +11 E92 -80,36 +13
KBS -54 +12 E70 -49 +12
-KW -48 +8 E24 -26 +13
KIMA +44 +72 E14 +44 +72
KEBL +36 +58 E3 +36 +58
KA +26 +56 E46 +26 +56
KD +5 +35 E60 +8 +35
KDR -21 +3 E52 -21 +3 (set FDORUN3)
FDORUN3 +38 +34 E120 +38 +34
These are "primary clocks". Variants are desired as follows:
KNPC = -K1+21??? KSTK = KIMA-4
-K1 = -K1IC KNPCSEL = KIMA+4
-K3IC = -K3 KBST = -K3-15 widened 15
KEBF = KBF delayed 8 -KALU = KBS+8
KBSI = KBS+50 KBEB = KBS delayed 30?
-KWIM = -KW+16 KEBL late = K1IC+KBSI-KBS
KI = KD advanced 17 widened 17
-KPE = KA
The cycle time constraints then are as follows:
C > 121 (interrupt stuff)
C > 131 (IMA+1 path)
C > 114 (STK mode controls)
C > 127 (INTDONE enabling -KIA)
C > 138 (P-mult controls)
C > 146 (P mask controls)
C > 127 (P←LM/RM)
C > 132 (Y adder stuff)
C > 122 (MDR/KMDR parity error logic)
C > 126 (-NOEXA between KEBL and -K3IC)
OLD PC BOARDS NEW PC BOARDS
C > 137 (NPC source, bipolar write)
C > 132 (NPC source, E-bus write)
C > 131 C > 121 (NPC read after NPC←)
C > 130 C > 125 (NPC read after IMA+1)
C > 152 C > 131 (bipolar read).
C > 124 C > 105 (ALUF, IPSEL decode).
C > 132 C > 114 (fast source decode).
C > 135 C > 111 (SRC, F1, DEST decode).
C > 137 C > 118 (IBREAK)
C > 136 C > 124 (B←ALU)
C > 135 C > 123 (ALUC1)
C > 140 C > 125 (NOT(ALU)Q RCY)
COMMENTS
1. -K2d must be early for freezing ALU output before new P clobbers output. However, this ALU constraint is less than bus driving.
2. Observed old bipolar read timing is about 15 better than analysis.
3. Typ F9309's are used for P-masking, typ I3404's for X and Y. This was not assumed in analysis, so P mask timing is 7 better than analysis, and bipolar read timing 3 better than analysis.
4. Typ F9312's for Y and advanced KA would improve timing for both bipolar reads and P.
5. With old bipolar boards, KBF↑ is constrained by bipolar writes, with new bipolar boards by E-bus writes.
CONCLUSIONS
With old bipolar boards, bipolar reads constrain the cycle time to about 150.
With new bipolar boards, P masking dominates for a cycle time of 145. If 82S23's are used for the mask ROM's, then a cycle time of about 137 is possible.
The relationship of the other clocks to these primary clocks is presently as follows:
-K1ICE = -K1IC advanced 5
K1ICE = K1IC advanced 7 widened 4
-K1IC* = -K1IC
-K1 = -K1IC advanced 2 widened 2
KP = -K1IC narrowed 2
-KP = -K1IC delayed 6 widened 3
-KP0 = -K1IC delayed 10 narrowed 3
KBL = -K1IC advanced 2 narrowed 3
KNPC = -K1IC delayed 15
KBUF1 = delayed 34 narrowed 2
KBF* = KBF delayed 2
KEBF = KBF delayed 8??????
KEBL = -K1IC ???
KEBLP = -K1IC delayed 2 narrowed 2
-K3IC = -K3 delayed 2 narrowed 3
KBST = -K3 advanced 12 widened 16
-KWIM = -KW delayed 14
KI = KD advanced 18 widened 15
KI* = KD advanced 20 widened 20
KBS* = KBS
KALU = KBS delayed 6 narrowed 3***should fix this
KBSI = KBS delayed 43 narrowed 10
KBEB = KBS delayed 28 narrowed 9
KA* = KA advanced 2
KSTK = KIMA advanced 4 widened 2
KIMA* = KIMA
-K2* = -K2 delayed 1 widened 1
-KNPCSEL = KIMA delayed 3
-NOEXBd = -K1↑+33, -NOEXB↑ = -K1↑+38
-NOEXd = -K3d+17, -NOEX↑ = -K3d+10
MORE OBSERVATIONS
The old bipolar boards are apparently quite sensitive to noise, so some effort must be made to keep input and output trash off its signals. The most sensitive uses of the old bipolar cards is IM boards 13 and 17, probably because of all the trash on the heavily loaded IFCN[xx] nets.
The CONTROL board is also very sensitive to noise, probably because of all the Schottky logic it uses. The incoming clocks have all been terminated and several are twisted pair on the card. The most sensitive nets are the PCBR and PCNOBR nets. Also the nets output from the S258-8T10 combinations.
The BEB card has been troublesome with noise also.
Very few of the cards can be extended with out making the machine inoperable.
If CONTROL continues to give trouble, consider duplicating PCBR and PCNOBR by developing another free can on the card and using that place for an H40.
Component Min Max Typical
H00, H04, H10, H20 5 10 6 Nand gates
S00, S04, S10, S20 3 5
LS00, LS04, LS10, LS20 20 10
H08, H11, H21, H30 6 12 7 And gates
S08 7.5 5
S11 3 7
N28 low to high out 9 6 Quad 2-in Nor
high to low out 12 8
M3002, M3003 6 12 7 Nor, Or gates
H40, M3026 6 12 7 hefty Nand, And gates
H51, H53, H54, H55, H50 6 11 And-Nor gates
H52 9 15 And-Or gates
S260 3 6 5-input Nor
S64 3 6
S86 5 10 7 2-input Xor gate
S280 6 21 14 9-input parity
F9348 PO output 48 40 12-in parity
PE output 55 47
N181 in to G/P 25 17 ALU chip
in to Cout 19 13
Cin to Cout 19 13
Cin to AnyF 19 13
S181 in to B/P 15 10.5
in to AnyF 30 20
Cin to Cout 10.5 7
in to Cout 23 15.5
Cin to AnyF 12 7
S182 G/Pin to Cout 7 Carry look-ahead
Cin to Cout 10.5
G/Pin to G/Pout 10.5
N283 Anyin to OUT 21 14 4-bit adder
IN to Cout 16 11
Cin to Cout 16 11
H87 B or C 25 17 4-bit true/complement
data 20 14
H183 18 12 dual 3-input adder
8T93 3 10 Hex Bus receiver
N368 17 Inverting bus buffer tristate output
N38 turn-on 18 11 Open-collector NAND
turn off 22 14
8T26 in-bus 20 Tristate driver/receiver
bus-out 18
enable-bus 43
8T26A Dout-Rout 14
Din-Dout 14
High-Z-0 (300 pf) 25
0-High-Z (300 pf) 20
8T09 in-out (30 pf) 10 Tristate bus driver
in-out (300 pf) 20
disable-out (300 pf) 22
8T97/8T95 ton 3 13 9 Hex bus driver
toff 3 12 7
1-hiZ 3 10 5
0-hiZ 3 12 6
hiZ-1 8 25 19
hiZ-0 12 25 14
8T98/8T96 ton 3 10 6
toff 3 11 7
1-hiZ 3 10 6
0-hiZ 3 16 10
hiZ-1 7 22 15
hiZ-0 11 24 18
Component Min Max Typical
H108 setup 13 Neg-edge trig ff
delay-out↑ 8 20 16
delay-outd 5 15 10
H74 clk width 15 Dual pos. edge trig ff
preset width 25
clear width 25
setup high in 10
setup low in 15
hold 0
delay-out↑ 4 15 8.5
delay-outd 7 20 13
S112 setup 3 Negative-edge-triggered ff
hold 0
delay 7
N174/5 setup 20
delay 35
hold 0
S174/5 setup 12
delay 17
LS174/5 data setup 20
clock width 20
data hold 5
ton from clock 30 21
LS163 clk width 25 4-bit pos. edge triggered synchronous counter
data, enP, clear setup 20
load setup 25
hold time 0
ripple carry 32 23
load delay 29 19
count delay 23 15
enT-r/c 16 11
clear delay 38 26
enT-r/c 16 11
clear-data 38 26
N194 setup control 30
hold 0
setup data 20
delay 26
N279/LS279 delayR 27 15 Quad set/reset flipflops
delayS 22 15
I3101A addr-out 10 35 16x4 bit RAM
select-out 5 17
writeclk 25
waddrsetup 0
wdatasetup 25
I3404 setup 12 Hex latch (write enable 12 pf)
clock-output 7 17
data-output 7 12
hold 8
8T10 clk-out (30 pf) 25 18 Quad D ff tristate outputs
clk-out (300 pf) 35 24
disable-output 30 20
hold 5 -1
setup data 5 -1
setup disable 0 -6
clock width 12 8 Rising edge triggered
8223 50 35 256-bit ROM
82S23 addr to out 40 25
enab to out 35 15
3107A writeclk 50 35 256 x 1 open-collector RAM
wsetup 60
whold 10
address-data 15 60 40
select-data 5 40 25
N82S10 writeclk 35 25 1024 x 1 open-collector RAM
wsetup-addr 5 0
wsetup-data 40 35
address-data 45 30
enable-data 30 15
disable-hiZ 30 15
Component Min Max Typical
F9309 data-Z 3 15 10 2 x 4-in selector
select-Z 23 17
data+Z 24 17
select+Z 32 24
F9312 data-Z 3 16 9 8-in selector
select-Z 9 26 18
enable-Z on 6 23 16
enable-Z off 6 20 14
S157 data 7.5 5 4 x 2-in selector
strobe 12.5 8.5
select 15 9.5
S158 data 6 4 Inverting 4 x 2-in selector
strobe 7
select 12 8
S258 data 6 4 Tristate 4 x 2-in selector
select 6 4
enable 21 14
disable from H 8.5 5.5
disable from L 14 9
F9318 data-enout↑ 2 15 8-in priority encoder
data-enoutd 7 25
en-group↑ 7 15
en-groupd 12 25
en-en↑ 7 15
en-end 14 32
en-data↑ 8 18
en-datad 10 25
data-group↑ 12 35
data-groupd 12 23
data-data↑ 11 25
data-datad 11 27
F9322
S151 select+Z 18 12 8-in selector
select-Z 15 10
data+Z 12 8
data-Z 7 4.5
enable+Z 18 12
enable-Z 13 9
I3205 5 18 1 out of 8 decoder