MTSChannelController.tioga
Created by beil Gunther, January 7, 1988 5:35:10 pm PST
Neil Gunther February 11, 1988 11:50:24 am PST
Neil Gunther: March 23, 1988 12:28:47 pm PST
IBM-PC Chip Tester:
Channel Control Card
Introduction
The following documentation refers to a design for an IBM-PC based chip tester. In particular, it describes a channel-controller card similar to that developed by Modular Test Systems (MTS).
Revision notes are provided at the end of this document.
Each card supports up to 64 fully bidirectional channels defined as [Channel0..Channel64].
These signals are controlled in groups of 8 by 8 banks defined as [Bank0..Bank7].
These signals are distributed in groups of 8 across 4 - 40 pin headers defined as [T1..T4].
Channel set and hold is achieved by use of the control signals: nLocalSet and nLocalOut.
Daisy-chaining of cards is achieved by use of the control signals: nChainSet and nChainOut.
Top level documentation is filed as:
[Spider Man:PARC]<GuntherDrawer>MTS>
MTSChannelController.doc --this document
MTS.df  2-page E format schematic
MTS.lib  private symbols & parts
MTS.dwg  IBM-PC expansion card form factor
For more information contact: Neil <Gunther.pa> or Gunther:PA:Xerox; Extn. 4401.
Headers
o Four, 40-pin channel headers.
o Pin sequencing:
Pin numbers alternate across the two rows (left -> right on component side of board).
2 4 6 ... etc. Signals are assigned to even pins.
1 3 5 ... etc. Ground is assigned to odd pins.
o Pin groupings are:
T1 = [
8 channels from Bank0,
8 channels from Bank1,
4 channels from Bank2
]
T2 = [
4 channels from Bank2,
8 channels from Bank3,
8 channels from Bank4
]
T3 = [
8 channels from Bank5,
8 channels from Bank6,
4 channels from Bank7
]
T4 = [
4 channels from Bank7,
8 configurable Control signals,
8 configurable as Vdd from IBM-PC power supply
]
o The driver software only uses the first 60 signals (currently).
o Header T4 is used to daisy-chain multiple cards in an IBM expansion chassis.
Parts Library
o PC Edge-connector
Row containing pin-1 needs to be mirrored.
o 40-pin Header
Check pin assignments.
o HCT Data Sheets
Check physical pin assignments.
o Part text
Ensure legible font size.
Mechanical Drawing
o IBM-PC Form Factor
Remove small edge connector in MTS.dwg.
o Wire-wrap Area
Remove wire-wrap patch area in MTS.dwg.
Placement of Components
o Four 40-pin headers (T1, T2, T3, T4) mounted inline along the top of the PC card.
o Horizontal ordering on the component-side of card: T4 (leftmost), T3, T2, T1 (rightmost).
o Headers should be oriented so that channel signals are assigned to the outboard row of pins with the GND pins assigned to the inboard row.
o Driver chips should be oriented, with respect to the 40-pin headers, such that pin 7 (GND) of the TTL package is adjacent to the the inboard row of header GND pins. (This reduces inductive resonance effects).
Components List
1  74HC08   Quad ANDs (used with common inputs as buffers)
1  74HCT04   Hex inverters
8  74HC126   Quad 3-state buffers
4  74HCT138  3 to 8 Mux
2  74HCT245  Octal bus xcvrs
24 74HCT273  Octal D-flop
8  74HCT374  Octal D-flop (tri-state outputs)
2  74HCT688  8-bit identity comparator
12 0.1 uF ceramics
4  10 uF Tantalum-B (replaces electrolytics)
4 40-pin headers
3 9-pin 47K SIP pull-ups
8 8-pin jumpers
2 4-pin jumpers
IBM card mounting brackets [FRY's Electronics (408) 733-1770]
Configuration Jumper Settings
Mem/IO addressing: P2-P3
P2-P3 pin 1 (nMEMR)
P2-P3 pin 3 (nMEMW)
Board address
Uses jumpers: J1 (Lo) and J2 (Hi)
Strapped jumper pin $ => 0 bit
Unstrapped jumper pin x  => 1 bit
SA0-3 used for DUT Read/Write command
SA4-11 Lo-order addr byte
SA12-19 Hi-order addr byte
Example addr location: CD01 {1100 1101 0000 0001} implies the following jumper settings:
J1 pin 1-8 {x$$$ $$$$}
J2 pin 1-8 {x$xx $$xx}
Local Set/Sense
P4-P5 pin 3 (nLocalSet)
P4-P5 pin 4 (nLocalOut)

Revision B
Rev. A prototype testing completed March 22, 1988.
WARNING:
Always check back-annotated schematic against data sheets before making tapes.
Modifications to Rev. A:
1. 74HCT688 (unavailable) replaced by 74FCT521 (apparently plug compatable).
2. 9-pin 47K SIP pull-ups replaced by 10-pin SIP.
3. Jumper holes enlarged to 42 mil because of square package pins.
4. T4 Header moved in from end of board to reduce physical interference.
5. Some Expert part names to be disambiguated.
6. Label Expert Tan-B caps. with + sign on Vdd pin.
7. Correct pin types for 74HCT688 logic symbol.
8. Correct the pin types/swap codes for 74HCT245 (B-A) logic symbol.
9. Decoupling caps for every HCT device.