IFUSchImpl.mesa
Copyright c 1985 by Xerox Corporation. All rights reserved.
Don Curry, April 21, 1987 6:53:17 pm PST
Last Edited by: Don Curry June 8, 1987 10:52:06 pm PDT
DIRECTORY Cabbage, Core, CoreCreate, CoreOps, DP, DragOpsCross, IFUSch, IO, PWCore, Route, TerminalIO;
IFUSchImpl:
CEDAR
PROGRAM
IMPORTS Cabbage, CoreCreate, CoreOps, DP, IO, PWCore, Route, TerminalIO
EXPORTS IFUSch
= BEGIN
IFUVersion: NAT = 2;
Wire: TYPE = Core.Wire;
Wires:
TYPE = Core.Wires;
LayoutWithOutCabbageSignals:
PUBLIC PWCore.LayoutProc = {
TerminalIO.PutF["\nBEGIN: LayoutWithOutCabbageSignals: %g\n", IO.time[]];
obj ← PWCore.Layout[cellType !
Cabbage.Signal =>
{TerminalIO.PutF["*** Cabbage Signal: %g\n", IO.rope[explanation]]; RESUME};
Route.Signal =>
{TerminalIO.PutF["*** Route Signal: %g\n", IO.rope[explanation]]; RESUME} ];
TerminalIO.PutF["\nEND: LayoutWithOutCabbageSignals: %g\n", IO.time[]]};
zero: Wire ← CoreOps.CreateWires[ size: 0, name: "Gnd"];
one: Wire ← CoreOps.CreateWires[ size: 0, name: "Vdd"];
Variable:
PROC[result, var: Wire, bias, scale:
INT] = {
first: NAT ← result.size - var.size;
WHILE scale>1 DO first ← first-1; scale←scale/2 ENDLOOP;
FOR i: NAT IN [0..var.size) DO result[first + i] ← var[i] ENDLOOP;
FOR i:
NAT
DECREASING
IN [0..result.size)
DO
IF (bias
MOD 2) = 1
THEN IF result[i]=NIL THEN result[i] ← one ELSE ERROR
ELSE IF result[i]=NIL THEN result[i] ← zero;
bias ← bias/2 ENDLOOP};
WireConst:
PUBLIC
PROC [val, size:
CARDINAL, name: Core.
ROPE ←
NIL]
RETURNS[wire: Core.Wire] = {
IF name=NIL THEN name ← IO.PutFR["Size%gConst%g", IO.int[size], IO.int[val]];
wire ← CoreOps.CreateWires[size, name];
FOR i:
NAT
DECREASING
IN [0..wire.size)
DO
wire[i] ← (IF (val MOD 2)=1 THEN one ELSE zero);
val ← val/2;
ENDLOOP};
Version:
PUBLIC
DP.WIProc =
{wire ← WireConst[IFUVersion, 8, "Version"]};
ABase:
PUBLIC
DP.WIProc =
{wire ← WireConst[DragOpsCross.ProcessorRegister[euAux].ORD, 8, "ABase"]};
CBase:
PUBLIC
DP.WIProc =
{wire ← WireConst[DragOpsCross.ProcessorRegister[euConstant].ORD, 8, "CBase"]};
NoStore:
PUBLIC
DP.WIProc =
{wire ← WireConst[DragOpsCross.ProcessorRegister[euJunk].ORD, 8, "NoStore"]};
FlagBubble:
PUBLIC
DP.WIProc = {
Byte: TYPE = [0..255];
ssw: DragOpsCross.StackedStatusWord ← [userMode: TRUE, trapsEnabled: FALSE];
bytes: PACKED ARRAY [0..4) OF Byte ← LOOPHOLE[ssw];
RETURN[WireConst[bytes[1], 8, "FlagBubble"]]};
MicroExcptJumps:
PUBLIC
DP.WIProc = {
StateBA: Core.Wire ← CoreOps.CreateWires[ size: 8, name: "StateBA"];
StateNormBA: Core.Wire ← CoreOps.CreateWires[ size: 8, name: "StateNormBA"];
StateDelayBA: Core.Wire ← CoreOps.CreateWires[ size: 8, name: "StateDelayBA"];
MicroJump: Core.Wire ← WireConst[48, 8, "MicroJump"];
Resetting: Core.Wire ← WireConst[112, 8, "Resetting"];
Trap: Core.Wire ← WireConst[116, 8, "Trap"];
CJump: Core.Wire ← WireConst[120, 8, "CJump"];
FOR i:
NAT
IN [0..8)
DO
StateBA[i] ←
StateNormBA[i] ←
StateDelayBA[i] ← CoreOps.CreateWires[0] ENDLOOP;
StateNormBA[0] ← zero;
StateDelayBA[0] ← one;
RETURN[CoreOps.CreateWire[
LIST[StateBA, StateNormBA, StateDelayBA, MicroJump, Resetting, Trap, CJump]]]};
Pipe0:
PUBLIC
DP.WIProc = {
wires: Core.Wires ←
LIST[
CoreOps.CreateWires[0, "EStkOverflow"],
CoreOps.CreateWires[0, "InstFault"],
CoreOps.CreateWires[0, "KIsRtOp"],
CoreOps.CreateWires[0, "FCtlIsRtOp"],
CoreOps.CreateWires[0, "Push"],
CoreOps.CreateWires[0, "Pop"],
CoreOps.CreateWires[0, "NX2ALitSrcNn"],
CoreOps.CreateWires[0, "xxx"] ];
wire ← CoreOps.CreateWire[ wires, "Pipe0"]};
Pipe1:
PUBLIC
DP.WIProc = {
EUAluOp: Wire ← CoreCreate.Seq[size: 4, name: "EUAluOp"];
wires: Core.Wires ←
LIST[
(EUAluOp[0] ← CoreOps.CreateWires[0]),
(EUAluOp[1] ← CoreOps.CreateWires[0]),
(EUAluOp[2] ← CoreOps.CreateWires[0]),
(EUAluOp[3] ← CoreOps.CreateWires[0]),
CoreOps.CreateWires[0, "EUWriteToPBus"],
CoreOps.CreateWires[0, "EUSt3AIsCBus"],
CoreOps.CreateWires[0, "InstStarting"],
CoreOps.CreateWires[0, "KPadsIn"] ];
wire ← CoreOps.CreateWire[ wires, "Pipe1"];
wire ← CoreOps.CreateWire[LIST[wire, EUAluOp]]};
Pipe2:
PUBLIC
DP.WIProc = {
CondEffect: Wire ← CoreCreate.Seq[size: 2, name: "CondEffect"];
EUCondSel: Wire ← CoreCreate.Seq[size: 4, name: "EUCondSel"];
wires: Core.Wires ←
LIST[
(EUCondSel[0] ← CoreOps.CreateWires[0]),
(EUCondSel[1] ← CoreOps.CreateWires[0]),
(EUCondSel[2] ← CoreOps.CreateWires[0]),
(EUCondSel[3] ← CoreOps.CreateWires[0]),
CoreOps.CreateWires[0, "DPCmndIsRd"],
CoreOps.CreateWires[0, "CIsField"],
(CondEffect[0] ← CoreOps.CreateWires[0]),
(CondEffect[1] ← CoreOps.CreateWires[0]) ];
wire ← CoreOps.CreateWire[ wires, "Pipe2"];
wire ← CoreOps.CreateWire[LIST[wire, CondEffect, EUCondSel]]};
XopGen:
PUBLIC
DP.WIProc = {
opAB: Wire ← CoreCreate.Seq[ size: 8, name: "OpAB"];
opGndAB: Wire ← CoreOps.CreateWires[ size: 32, name: "OpGndAB"];
xopPC: Wire ← CoreOps.CreateWires[ size: 32, name: "XopPC"];
wire ← CoreOps.CreateWire[LIST[opGndAB, xopPC]];
Variable[
result: opGndAB,
var: opAB,
bias: 0,
scale: 1000000h];
Variable[
result: xopPC,
var: opAB,
bias: DragOpsCross.bytesPerWord * DragOpsCross.XopBase,
scale: DragOpsCross.bytesPerWord * DragOpsCross.TrapWidthWords]};
TrapGen:
PUBLIC
DP.WIProc = {
except: Wire ← CoreCreate.Seq[ size: 4, name: "ExceptCodeAB"];
cond: Wire ← CoreCreate.Seq[ size: 4, name: "EUCondSel3AB"];
fault: Wire ← CoreCreate.Seq[ size: 3, name: "DPFaultCodeAB"];
exceptPC: Wire ← CoreOps.CreateWires[ size: 32, name: "ExceptPCB"];
condPC: Wire ← CoreOps.CreateWires[ size: 32, name: "CondPCB"];
faultPC: Wire ← CoreOps.CreateWires[ size: 32, name: "FaultPCB"];
publics: Wires ← LIST[except, cond, fault, exceptPC, condPC, faultPC];
bias: INT ← DragOpsCross.bytesPerWord * DragOpsCross.TrapBase;
scale: INT ← DragOpsCross.bytesPerWord * DragOpsCross.TrapWidthWords;
Variable[result: exceptPC, var: except, bias: bias + scale*00B, scale: scale];
Variable[result: condPC, var: cond, bias: bias + scale*20B, scale: scale];
Variable[result: faultPC, var: fault, bias: bias + scale*40B, scale: scale];
wire ← CoreOps.CreateWire[publics]};
Dual:
PUBLIC
DP.WIProc = {
wires: Core.Wires ←
LIST[
CoreOps.CreateWires[0, "DualHi"],
CoreOps.CreateWires[0, "DualLow"] ];
wire ← CoreOps.CreateWire[ wires, "Dual"]};
DP.RegisterWI["Version.icon", Version];
DP.RegisterWI["ABase.icon", ABase];
DP.RegisterWI["CBase.icon", CBase];
DP.RegisterWI["NoStore.icon", NoStore];
DP.RegisterWI["FlagBubble.icon", FlagBubble];
DP.RegisterWI["MicroExcptJumps.icon", MicroExcptJumps];
DP.RegisterWI["XopGen.icon", XopGen];
DP.RegisterWI["TrapGen.icon", TrapGen];
DP.RegisterWI["Dual.icon", Dual];
DP.RegisterWI["Pipe0.icon", Pipe0];
DP.RegisterWI["Pipe1.icon", Pipe1];
DP.RegisterWI["Pipe2.icon", Pipe2];
END.