<<IFUNotes.tioga>>
<<Don Curry December 7, 1987 3:58:06 pm PST>>
1304/8 = 163
ControlColumn Drivers
AP AG BP BG
Left
16 16
4
7 4
10 9
9 6
48 48
16
3 6
3 8
5
20 3 25 1
18
Right
37
22
16
22
19
16
16
4 21
13 3 23
Driver Totals
102 84 316 5
Pads
phA phB
64 32
DataColumn
phA phB NphA NphB
4 5 (* 5 Latches) FetchIndexing and StackIndexing
1 (* 8 Latches) ABForm
3- 2 (* 32 Latches) InstrReg
4 8 (* 32 Latches) PCForm
2 (* 32 Latches) Stack
1 4 (* 32 Latches) LSForm
2 (* 32 Latches) ABForm
3 (* 32 Latches) ControlPipe
2- (* 32 PreChg) InstrReg
2 (* 32 PreChg) Stack
1 (* 32 PreChg) ABForm
1 (* 32 DisChrg) ABForm
1 1 (* 32 TriDr) ABForm
DataColumn Totals
348 633 (* Latches)
32 128 (* PreChg)
32 (* DisChrg)
32 32 (* TriDr)
Routing
General
phA 8 * 8 mm
phB 8 * 8 mm
NphA 6 * 8 mm
NphB 6 * 8 mm
DataPath
phA 15*4 mm
phB 26*4 mm
NphA 1*4 mm
NphB 5*4 mm
Routing Totals
phA 124 mm
phB 168 mm
NphA 52 mm
NphB 68 mm
Gate Sizes
Dr Gate 36 micron gate
Dr pass n 8 micron gate
Dr pass p 10 micron gate
Pads 42 micron gate
Latch 8 micron gate
DPPreChg 16 micron gate
DPDisChg 28 micron gate
DPTriDr 44 micron gate
Capacitance
Routing .2 pF /mm
gate .0025 pF /micron = 1/400
Driver Totals
AP AG BP BG
102 84 316 5
PhA = 102*(8/400) = 2
NPhA = 102*(10/400) = 2.5
PhB = 316*(8/400) = 6.5
NPhB = 316*(10/400) = 8
PhA = 84*(36/400) = 8
PhB = 5*(36/400) = -
Pads
phA phB
64 = 7 32 = 3.5
DataColumn Totals
phA phB NphA NphB
348 633 (* Latches) 8
32 128 (* PreChg) 16
32 (* DisChrg) 28
32 32 (* TriDr) 44
Routing Totals
phA 124 mm
phB 168 mm
NphA 52 mm
NphB 68 mm
Gates Gates Gates
CC DP Pads Rout Total
PhA 10 7 7 25 50
PhB 6.5 18.5 3.5 33 62
NPhA 2.5 1 10.5 13
NPhB 8 9 13 30
60 pF 18 ohms *2 => 2.2 ns
36000/18 = 2000 microns of n type gate on last stage
Layout StackIndexingMain
640 transistors
Data Path Rows: StackIndexingMain
17 x1: 480 x2: 960 y1: 3136 y2: 3264 Mux StackAdjMux
16 x1: 480 x2: 960 y1: 2784 y2: 3136 SB
15 x1: 480 x2: 960 y1: 2400 y2: 2784 DPFullAdder
14 x1: 480 x2: 960 y1: 2240 y2: 2368 Mux PreTosAMux
13 x1: 480 x2: 960 y1: 2080 y2: 2208 Mux PreBosAMux
12 x1: 480 x2: 960 y1: 1920 y2: 2052 DPBuf
11 x1: 480 x2: 960 y1: 1760 y2: 1892 DPBuf
10 x1: 480 x2: 960 y1: 1632 y2: 1760 SB
9 x1: 480 x2: 960 y1: 1504 y2: 1632 Mux TosAMux
8 x1: 480 x2: 960 y1: 1344 y2: 1472 Mux BosAMux
7 x1: 480 x2: 960 y1: 1184 y2: 1316 DPLatch
6 x1: 480 x2: 960 y1: 1024 y2: 1156 DPLatch
5 x1: 480 x2: 960 y1: 864 y2: 996 DPInv
4 x1: 480 x2: 960 y1: 704 y2: 864 SB
3 x1: 480 x2: 960 y1: 320 y2: 704 DPFullAdder
2 x1: 480 x2: 960 y1: 160 y2: 292 DPLatch
1 x1: 480 x2: 960 y1: 0 y2: 132 DPLatch
0 x1: 480 x2: 960 y1: -160 y2: -28 DPLatch
Layout Size (lambda) x: 600 y: 721 xy: 432600
Layout DeltaS
190 transistors
Data Path Rows: DeltaS
3 x1: 480 x2: 960 y1: 752 y2: 894 SB
2 x1: 480 x2: 960 y1: 368 y2: 752 DPFullAdder
1 x1: 480 x2: 960 y1: 196 y2: 368 SB
0 x1: 480 x2: 960 y1: 64 y2: 196 DPBuf
Layout Size (lambda) x: 600 y: 199 xy: 119400
Layout FetchIndexingMain
750 transistors
Data Path Rows: FetchIndexingMain
16 x1: 480 x2: 960 y1: 3424 y2: 3838 SB
15 x1: 480 x2: 960 y1: 3040 y2: 3424 DPFullAdder
14 x1: 480 x2: 960 y1: 2912 y2: 3040 SB
13 x1: 480 x2: 960 y1: 2752 y2: 2912 Mux FetchWtBMux
12 x1: 480 x2: 960 y1: 2592 y2: 2724 DPLatch
11 x1: 480 x2: 960 y1: 2432 y2: 2564 DPLatch
10 x1: 480 x2: 960 y1: 2240 y2: 2432 SB
9 x1: 480 x2: 960 y1: 1856 y2: 2240 DPFullAdder
8 x1: 480 x2: 960 y1: 1696 y2: 1856 SB
7 x1: 480 x2: 960 y1: 1536 y2: 1696 Mux FetchRdBMux
6 x1: 480 x2: 960 y1: 1376 y2: 1508 DPLatch
5 x1: 480 x2: 960 y1: 1216 y2: 1348 DPLatch
4 x1: 480 x2: 960 y1: 1056 y2: 1188 DPInv
3 x1: 480 x2: 960 y1: 864 y2: 1056 SB
2 x1: 480 x2: 960 y1: 480 y2: 864 DPFullAdder
1 x1: 480 x2: 960 y1: 320 y2: 452 DPLatch
0 x1: 480 x2: 960 y1: 2 y2: 320 SB
Layout Size (lambda) x: 600 y: 761 xy: 456600
Stack layout attributes for LeftColumn
Right justified Y stack, max width: 9488
Channel
Abut min:-3400 max: 6088
10 off: 0 width: 6088 height: 4800 FetchIndexingRot90.sch
Channel
Abut min:-2624 max: 6864
9 off: 128 width: 6736 height: 4832 FetchRdDecode
8 off: 1088 width: 5776 height: 2336 FetchWtDecode
7 off:-1472 width: 8336 height: 7520 FetchControl
6 off:-1408 width: 8272 height:18080 StackDecode
5 off: 768 width: 6096 height: 2720 StackControlA
4 off: 512 width: 6352 height: 3232 StackControlB
3 off: 2336 width: 4528 height: 1088 LtDrPadIO
2 off:-2624 width: 9488 height: 9824 MainPipeControl
1 off: 0 width: 6864 height: 4448 Interlock
Channel
Abut min:-2128 max: 7360
0 off: 0 width: 7360 height: 4800 StackIndexingRot90.sch
Channel
Stack layout attributes for RightColumn
Left justified Y stack, max width: 11408
Channel
Abut min: 0 max:11408
3 off: 0 width:11008 height:11520 LogoJune87.icon
Channel
Abut min: 0 max:11408
2 off: 0 width:11408 height:41952 RightControl
1 off: 0 width: 4528 height: 7040 RtDrPadIOFlipX
Channel
Abut min: 0 max:11408
0 off: 0 width:11200 height: 2688 ClockBuf
Channel
Layout FetchAddr
2252 transistors
Data Path Rows: FetchAddr
8 x1: 480 x2: 960 y1: 2128 y2: 2260 DPBuf
7 x1: 480 x2: 960 y1: 1732 y2: 2128 SB
6 x1: 480 x2: 960 y1: 1440 y2: 1732 DPAdderGPC
5 x1: 480 x2: 960 y1: 1252 y2: 1440 SB
4 x1: 480 x2: 960 y1: 832 y2: 1252 DPAdderSum
3 x1: 480 x2: 960 y1: 672 y2: 804 DPLatch
2 x1: 480 x2: 960 y1: 480 y2: 640 Mux FetchAddrBMux
1 x1: 480 x2: 960 y1: 320 y2: 452 DPLatch
0 x1: 480 x2: 960 y1: 2 y2: 320 SB
Layout Size (lambda) x: 3840 y: 698 xy: 2680320
Layout FetchInst
Warning: Zero transistor celltype: DPLatchBlank
Warning: Zero transistor celltype: DPLatchBlank
400 transistors
Data Path Rows: FetchInst
3 x1: 480 x2: 2400 y1: 640 y2: 740 DPPreChg
2 x1: 480 x2: 2400 y1: 480 y2: 612 DPLatch
1 x1: 480 x2: 2400 y1: 320 y2: 452 DPLatchPreChg
0 x1: 480 x2: 2400 y1: 2 y2: 320 SB
Layout Size (lambda) x: 3840 y: 314 xy: 1205760
Layout XaForm
1120 transistors
Data Path Rows: XaForm
5 x1: 480 x2: 2400 y1: 960 y2: 1184 Mux XaPipeAB0Mux
4 x1: 480 x2: 2400 y1: 800 y2: 932 DPLatch
3 x1: 480 x2: 2400 y1: 640 y2: 772 DPLatch
2 x1: 480 x2: 2400 y1: 480 y2: 612 DPLatch
1 x1: 480 x2: 2400 y1: 288 y2: 452 DPTriDr
0 x1: 480 x2: 2400 y1: 2 y2: 288 SB
Layout Size (lambda) x: 3840 y: 209 xy: 802560
Layout PCFormTop
2720 transistors
Data Path Rows: PCFormTop
17 x1: 480 x2: 960 y1: 3600 y2: 3764 DPTriDr
16 x1: 480 x2: 960 y1: 3088 y2: 3600 SB
15 x1: 480 x2: 960 y1: 2928 y2: 3088 Mux TrapPCMux
14 x1: 480 x2: 960 y1: 2736 y2: 2868 DPLatch
13 x1: 480 x2: 960 y1: 2544 y2: 2708 DPTriDr
12 x1: 480 x2: 960 y1: 2352 y2: 2516 DPTriDr
11 x1: 480 x2: 960 y1: 2160 y2: 2324 DPTriDr
10 x1: 480 x2: 960 y1: 1776 y2: 2160 SB
9 x1: 480 x2: 960 y1: 1584 y2: 1776 Mux PCBrOSetABMux
8 x1: 480 x2: 960 y1: 1424 y2: 1556 DPLatch
7 x1: 480 x2: 960 y1: 1248 y2: 1392 Mux PCBranchMux
6 x1: 480 x2: 960 y1: 1088 y2: 1220 DPBuf
5 x1: 480 x2: 960 y1: 928 y2: 1060 DPLatch
4 x1: 480 x2: 960 y1: 644 y2: 928 SB
3 x1: 480 x2: 960 y1: 512 y2: 644 DPLatch
2 x1: 480 x2: 960 y1: 320 y2: 480 Mux PCAMux
1 x1: 480 x2: 960 y1: 160 y2: 292 DPLatch
0 x1: 480 x2: 960 y1: -32 y2: 132 DPTriDr
Layout Size (lambda) x: 3840 y: 722 xy: 2772480
Layout PCFormBot
5324 transistors
Data Path Rows: PCFormBot
21 x1: 480 x2: 960 y1: 3968 y2: 4100 DPLatch
20 x1: 480 x2: 960 y1: 3748 y2: 3968 SB
19 x1: 480 x2: 960 y1: 3456 y2: 3748 DPAdderGPC
18 x1: 480 x2: 960 y1: 3236 y2: 3456 SB
17 x1: 480 x2: 960 y1: 2816 y2: 3236 DPAdderSum
16 x1: 480 x2: 960 y1: 2656 y2: 2788 DPLatch
15 x1: 480 x2: 960 y1: 2464 y2: 2628 DPTriDr
14 x1: 480 x2: 960 y1: 2400 y2: 2464 SB
13 x1: 480 x2: 960 y1: 2240 y2: 2400 Mux PCAltPipe1AMux
12 x1: 480 x2: 960 y1: 2080 y2: 2212 DPLatch
11 x1: 480 x2: 960 y1: 1920 y2: 2052 DPLatch
10 x1: 480 x2: 960 y1: 1760 y2: 1892 DPLatch
9 x1: 480 x2: 960 y1: 1600 y2: 1732 DPLatch
8 x1: 480 x2: 960 y1: 1440 y2: 1572 DPLatch
7 x1: 480 x2: 960 y1: 1280 y2: 1412 DPLatch
6 x1: 480 x2: 960 y1: 1120 y2: 1252 DPLatch
5 x1: 480 x2: 960 y1: 960 y2: 1092 DPLatch
4 x1: 480 x2: 960 y1: 800 y2: 928 Mux PCPipe3AMux
3 x1: 480 x2: 960 y1: 640 y2: 772 DPLatch
2 x1: 480 x2: 960 y1: 480 y2: 612 DPLatch
1 x1: 480 x2: 960 y1: 288 y2: 452 DPTriDr
0 x1: 480 x2: 960 y1: 96 y2: 260 DPTriDr
Layout Size (lambda) x: 3840 y: 1147 xy: 4404480
Layout PCStkIO
832 transistors
Data Path Rows: PCStkIO
7 x1: 480 x2: 960 y1: 1152 y2: 1278 SB
6 x1: 480 x2: 960 y1: 1024 y2: 1152 Mux PrePCStackWtDataAMux
5 x1: 480 x2: 960 y1: 864 y2: 996 DPBuf
4 x1: 480 x2: 960 y1: 672 y2: 836 DPTriDr
3 x1: 480 x2: 960 y1: 512 y2: 644 DPLatch
2 x1: 480 x2: 960 y1: 352 y2: 480 Mux SelPCStackRdDataAMux
1 x1: 480 x2: 960 y1: 192 y2: 324 DPInv
0 x1: 480 x2: 960 y1: 64 y2: 164 DPPreChg
Layout StatStkIO
832 transistors
Data Path Rows: StatStkIO
7 x1: 480 x2: 960 y1: 1072 y2: 1172 DPPreChg
6 x1: 480 x2: 960 y1: 912 y2: 1044 DPInv
5 x1: 480 x2: 960 y1: 752 y2: 880 Mux SelStatStackRdDataAMux
4 x1: 480 x2: 960 y1: 592 y2: 724 DPLatch
3 x1: 480 x2: 960 y1: 400 y2: 564 DPTriDr
2 x1: 480 x2: 960 y1: 240 y2: 372 DPBuf
1 x1: 480 x2: 960 y1: 80 y2: 208 Mux PreStatStackWtDataAMux
0 x1: 480 x2: 960 y1: -126 y2: 80 SB
Layout Size (lambda) x: 3840 y: 232 xy: 890880
Layout LSFormTop
1680 transistors
Data Path Rows: LSFormTop
12 x1: 480 x2: 2400 y1: 3600 y2: 3838 SB
11 x1: 480 x2: 2400 y1: 3312 y2: 3600 Mux CTopArgMux
10 x1: 480 x2: 2400 y1: 3088 y2: 3280 Mux STopArgMux
9 x1: 480 x2: 2400 y1: 2864 y2: 3056 Mux LTopArgMux
8 x1: 480 x2: 2400 y1: 2164 y2: 2864 SB
7 x1: 480 x2: 2400 y1: 1872 y2: 2164 DPAdderGPC
6 x1: 480 x2: 2400 y1: 1652 y2: 1872 SB
5 x1: 480 x2: 2400 y1: 1232 y2: 1652 DPAdderSum
4 x1: 480 x2: 2400 y1: 1008 y2: 1232 SB
3 x1: 480 x2: 2400 y1: 784 y2: 1008 Mux CBotArgMux
2 x1: 480 x2: 2400 y1: 560 y2: 752 Mux SBotArgMux
1 x1: 480 x2: 2400 y1: 336 y2: 528 Mux LBotArgMux
0 x1: 480 x2: 2400 y1: 2 y2: 336 SB
Layout Size (lambda) x: 3840 y: 889 xy: 3413760
Layout LSFormBot
2432 transistors
Data Path Rows: LSFormBot
19 x1: 480 x2: 2400 y1: 3168 y2: 3296 Mux CSumxMux
18 x1: 480 x2: 2400 y1: 2944 y2: 3136 Mux FlagBMux
17 x1: 480 x2: 2400 y1: 2852 y2: 2944 SB
16 x1: 480 x2: 2400 y1: 2720 y2: 2852 DPLatch
15 x1: 480 x2: 2400 y1: 2560 y2: 2692 DPLatch
14 x1: 480 x2: 2400 y1: 2400 y2: 2532 DPLatch
13 x1: 480 x2: 2400 y1: 2240 y2: 2372 DPLatch
12 x1: 480 x2: 2400 y1: 1920 y2: 2052 DPLatch
11 x1: 480 x2: 2400 y1: 1792 y2: 1920 SB
10 x1: 480 x2: 2400 y1: 1664 y2: 1792 Mux C2AMux
9 x1: 480 x2: 2400 y1: 1504 y2: 1636 DPLatch
8 x1: 480 x2: 2400 y1: 1376 y2: 1504 SB
7 x1: 480 x2: 2400 y1: 1248 y2: 1376 Mux C2BMux
6 x1: 480 x2: 2400 y1: 1088 y2: 1220 DPLatch
5 x1: 480 x2: 2400 y1: 928 y2: 1088 SB
4 x1: 480 x2: 2400 y1: 800 y2: 928 Mux C3AMux
3 x1: 480 x2: 2400 y1: 640 y2: 772 DPLatch
2 x1: 480 x2: 2400 y1: 512 y2: 640 SB
1 x1: 480 x2: 2400 y1: 384 y2: 512 Mux C3BMux
0 x1: 480 x2: 2400 y1: 224 y2: 356 DPLatch
Layout Size (lambda) x: 3840 y: 594 xy: 2280960
Layout ABFormMain
3320 transistors
Data Path Rows: ABFormMain
27 x1: 480 x2: 2400 y1: 6464 y2: 6654 SB
26 x1: 480 x2: 2400 y1: 6176 y2: 6464 Mux ABRegRtArgMux
25 x1: 480 x2: 2400 y1: 5856 y2: 6144 Mux ABRegRtArgMux
24 x1: 480 x2: 2400 y1: 5252 y2: 5856 SB
23 x1: 480 x2: 2400 y1: 4960 y2: 5252 DPAdderGPC
22 x1: 480 x2: 2400 y1: 4740 y2: 4960 SB
21 x1: 480 x2: 2400 y1: 4320 y2: 4740 DPAdderSum
20 x1: 480 x2: 2400 y1: 4064 y2: 4320 SB
19 x1: 480 x2: 2400 y1: 3840 y2: 4064 Mux BRegLtArgMux
18 x1: 480 x2: 2400 y1: 3584 y2: 3808 Mux ARegLtArgMux
17 x1: 480 x2: 2400 y1: 3392 y2: 3584 SB
16 x1: 480 x2: 2400 y1: 3264 y2: 3392 Mux ABSumxMux
15 x1: 480 x2: 2400 y1: 3104 y2: 3232 Mux ABSumxMux
14 x1: 480 x2: 2400 y1: 2912 y2: 3072 Mux StateBMux
13 x1: 480 x2: 2400 y1: 2752 y2: 2884 DPLatch
12 x1: 480 x2: 2400 y1: 2528 y2: 2752 SB
11 x1: 480 x2: 2400 y1: 2272 y2: 2528 Mux StateAMux
10 x1: 480 x2: 2400 y1: 2180 y2: 2272 SB
9 x1: 480 x2: 2400 y1: 2048 y2: 2180 DPLatch
8 x1: 480 x2: 2400 y1: 1728 y2: 1856 Mux AB1BMux
7 x1: 480 x2: 2400 y1: 1412 y2: 1728 SB
6 x1: 480 x2: 2400 y1: 1280 y2: 1412 DPLatch
5 x1: 480 x2: 2400 y1: 1120 y2: 1252 DPXOr
4 x1: 480 x2: 2400 y1: 960 y2: 1092 DPDisChg
3 x1: 480 x2: 2400 y1: 832 y2: 932 DPPreChg
2 x1: 480 x2: 2400 y1: 452 y2: 832 SB
1 x1: 480 x2: 2400 y1: 288 y2: 452 DPTriDr
0 x1: 480 x2: 2400 y1: 96 y2: 260 DPTriDr
Layout Size (lambda) x: 3840 y: 1364 xy: 5237760
Layout ControlPipeMain
2000 transistors
Data Path Rows: ControlPipeMain
15 x1: 576 x2: 2496 y1: 4560 y2: 5374 SB
14 x1: 576 x2: 2496 y1: 4432 y2: 4560 Mux DPCmnd0BMux
13 x1: 576 x2: 2496 y1: 4272 y2: 4400 Mux EUCondSel0BMux
12 x1: 576 x2: 2496 y1: 4112 y2: 4240 Mux EUAluOp0BMux
11 x1: 576 x2: 2496 y1: 3936 y2: 4068 DPLatchOr
10 x1: 576 x2: 2496 y1: 2308 y2: 3936 SB
9 x1: 576 x2: 2496 y1: 2176 y2: 2308 DPLatch
8 x1: 576 x2: 2496 y1: 2016 y2: 2148 DPLatch
7 x1: 576 x2: 2496 y1: 1824 y2: 1952 Mux ControlPipe02AMux
6 x1: 576 x2: 2496 y1: 1664 y2: 1796 DPLatch
5 x1: 576 x2: 2496 y1: 1504 y2: 1632 Mux ControlPipe02BMux
4 x1: 576 x2: 2496 y1: 1344 y2: 1476 DPLatch
3 x1: 576 x2: 2496 y1: 464 y2: 1344 SB
2 x1: 576 x2: 2496 y1: 336 y2: 464 Mux ControlPipe03AMux
1 x1: 576 x2: 2496 y1: 176 y2: 308 DPLatch
0 x1: 576 x2: 2496 y1: 16 y2: 148 DPLatch
Layout Size (lambda) x: 3840 y: 906 xy: 3479040
Stack layout attributes for IFUInner
Top justified X stack, max width: 72160
Abut min: 0 max:72160
2 off: 0 width:72160 height:11408 RightColumn
Channel
Abut min:-1304 max:70856
1 off: 0 width:70856 height:33024 DataColumn
Channel
Abut min:-1760 max:70400
0 off: 0 width:70400 height: 9488 LeftColumn
Notes: January 25, 1985 10:09:23 am PST
<<
noBypassing
passrt
>>
<<Let dump dEXCH. It's odd, requires a unique output and doesn't help much.>>
<<instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dEXCH]]];>>
<<Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[>>
<<dontGetNextMacro: TRUE,>>
<<bReg: abStackTop,>>
<<cReg: [ s, minus1 ] ] ];>>
<<Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[>>
<<noBypassing: TRUE,>>
<<bReg: [ s, minus1 ],>>
<<cReg: cStackTop ]];>>
Notes: January 23, 1985 2:32:54 pm PST
POUT and PIN are OUT and IN with beta47 supplying the epCmnd
POUT and PIN are ODB's
condcode=kernal <= epCmnd=*fetch* and usermode
Check DragOps.tioga execution times
DragOpsCross.Inst[dKFC]
DragOpsCross.Inst[dRETK] RETT
DragOpsCross.Inst[dLIP] LIFUR
DragOpsCross.Inst[dSIR] SIFUR
DragOpsCross.Inst[dSFP] FP
DragOpsCross.Inst[dFLOP] -- no FLIP change DragonFP and DragOps.tioga
FLOP
Alpha[1] 0 => Result to Stack
1 => Result to Internal A register
Beta[0..1] 0 => no B operand; fpAdjust_0
1 => B operand is single REAL; fpAdjust_1
2 => B operand is double REAL; fpAdjust_2
3 => B operand is single INT; fpAdjust_1 ??
How about changing pushpending/poppending/empty to WillBeEmpty/ReturnReady
Status
trap/usermode changes at lev 0 (and need restart from lev 3)
reschedule changes at lev 3
fp changes at lev 3
Status must watch fp Shadow cAddrs
FPControl must use WtMode (cAddr match) to also or with CSWtAlt/Mult
Remember to include fpEnable pin
These two can be generated in the PLA or at end
out.kIsRtOp _ out.xaSource IN [alpha..bReg] AND (out.aluOp # FOPK);
out.DrKaLev2 _ out.xaSource IN [alpha..bReg] or fp..... See notes;
Notes: January 21, 1985 1:50:59 pm PST
Remove PCNext from InstrDecodeOut
pcNext-Is-pcBus _ macroJump OR dontGetNextMacro;
Mode change could be simply SPR to ifuFPModeAlu or ifuFPModeMult if there were not the requirement to catch fp ops in the case
where the fpEnable pin is not true.
Notes: January 18, 1985 4:23:02 pm PST
Reorder traps - IFUPLA.ExceptionCode
trap expansions for cTrap fpFault epFault
4 bit Dragon.PBusFaults
Redefinition of Dragon.PBusFaults
PBusFaults: TYPE = MACHINE DEPENDENT {
FPeqZeroE, FPlsInfE, FPgrNEZeroE, FPneZeroI,
FPres4, FPoFlowI, FPuFlow, FPuFlowI,
FPaDeNorm, FPbDeNorm, FPabDeNorm, FPdivByZero,
FPaNaN, FPbNaN, FPabNaN, FPinvalid};
None: PBusFaults = FPeqZeroE;
Page: PBusFaults = FPlsInfE;
Write: PBusFaults = FPgrNEZeroE;
Redefinition of Dragon.PBusCommands
PBusCommands: TYPE = MACHINE DEPENDENT {NoOp(0), Reserve1(1), FPLdAlu(2), FPLdMult(3), FPUnAlu(4), FPUnMult(5), FPXfrMult(6),
FPXfrMult(7), Store(8), Fetch(9), StoreHold(10), FetchHold(11), IOStore(12), IOFetch(13), IOStoreHold(14), IOFetchHold(15)};
0000 NoOp
0001
0010 FPLdAlu CSLd 3 XaDr 3 euWt
0011 FPLdMult CSLd 3 XaDr 3 euWt
0100 FPUnAlu CSUn 2 XaDr 2 NoCheckParity
0101 FPUnMult CSUn 2 XaDr 2 NoCheckParity
0110 FPXfrAlu CSUn 2 XaDr 2 3 NoCheckParity
0111 FPXfrMult CSUn 2 XaDr 2 3 NoCheckParity
1000 Store
1001 Fetch
1010 StoreHold
1011 FetchHold
1100 IOStore
1101 IOFetch
1110 IOStoreHold
1111 IOFetchHold
CSUnAlu _ FPUnAlu OR FPXfrAlu
CSUnMult _ FPUnMult OR FPXfrMult
CSLdAlu _ FPLdAlu OR FPXfrAlu OR Caddr fpModeAlu
CSLdMult _ FPUnMult OR FPXfrMult OR Caddr fpModeMult
XaDr2 _ FPUnAlu .. FPXfrMult OR XaSource abgd..alpha
XaDr3 _ FPLdAlu .. FPLdMult, OR FPXfrAlu .. FPXfrMult
euDrPBus _ FPLdAlu .. FPLdMult OR *Store*
CheckParity _ *Fetch*
<<>>
<<IFUPLA.XaSource>>
<<This is essentially the Load-Unload code for the Weitek chips with alpha-beta-gamma-delta selection stuck into gaps in the
encoding. See DragonIFU33.sil>>
<<Note: alpha-beta-gamma-delta selection must => DrXa2>>
XaSource: TYPE = MACHINE DEPENDENT {
none(00B),
fpLdSglBSt(06B), fpLdLswBSt(12B), fpLdMswBSt(16B),
delGamBetAlp(20B), betaAlpha(21B), beta(22B), alpha(23B),
fpLdSglAUnMsw(25B), fpLdLswAUnLsw(30B), fpLdMswAUnMsw(35B), res31(37B)};
ProcessorRegister: TYPE = MACHINE DEPENDENT {
euJunk (128), -- the non-matching EU register
<< (129)>>
euMAR (130), -- MemoryAddressRegister
euField (131), -- Field register
fpAluClear (132), -- Base of FP Alu shadow Regs can alias 134 in EU
fpAluSgl (133), -- Single precision shadow can alias 135 in EU
fpAluLsw (134), -- Double precision Lsw shadow can alias 132 in EU
fpAluMsw (135), -- Double precision Msw shadow can alias 133 in EU
<< (136)>>
<< (137)>>
<< (138)>>
<< (139)>>
fpMultClear (140), -- Base of FP Mult shadow Regs can alias 142 in EU
fpMultSgl (141), -- Single precision shadow can alias 143 in EU
fpMultLsw (142), -- Double precision Lsw shadow can alias 140 in EU
fpMultMsw (143), -- Double precision Msw shadow can alias 141 in EU
euConstant (144), -- Base of EU constant registers (12 regs)
<< (156)>>
<< (157)>>
<< (158)>>
<< (159)>>
euAux (160), -- Base of EU aux registers (16 regs)
euBogus (176), -- [euBogus..euLast] not legal (NA) (63 regs)
euLast (239), -- last possible EU reg (NA)
ifuXBus (240), -- Base for IFU regs
ifuStatus (241), -- IFU status
ifuFPModeAlu (242), -- floating point mode register
ifuFPModeMult (243), -- floating point mode register
ifuFPMaskFlags (244), -- floating point mask and flags
ifuSLimit (245), -- stack limit register
ifuYoungestL (246), -- youngest L in IFU stack
ifuYoungestPC (247), -- youngest PC in IFU stack
ifuEldestL (248), -- eldest L in IFU stack
ifuEldestPC (249), -- eldest PC in IFU stack (rd removes, wt adds)
<< (250)>>
ifuBogus (251), -- [ifuBogus..ifuLast] are not legal (NA)
ifuL (252), -- current L register (NA)
ifuS (253), -- current S register (NA)
ifuPC (254), -- current program counter (NA)
ifuLast (255)};-- last possible IFU reg (NA)
IFUPLA
32 KBus = INT[32], -- PhA bidirectional, PhB A,B,C to EU
02 EUAluLeftSrcBA > EnumType["Dragon.ALULeftSources"],
02 EUAluRightSrcBA > EnumType["Dragon.ALURightSources"],
02 EUStore2ASrcBA > EnumType["Dragon.Store2ASources"],
05 EUAluOpAB > EnumType["Dragon.ALUOps"],
04 EUCondSelAB > EnumType["Dragon.CondSelects"],
01 EUHoldCarryBA > BOOL,
01 EUSt3AisCBusBA > BOOL,
01 EURes3AisCBusBA > BOOL,
01 EUConditionBA < BOOL,
01 EURes3BisPBusAB > BOOL,
01 EUWriteToPBusAB > BOOL,
01 EUCheckPParityAB > BOOL,
---
22
04 FPStatusB <EnumType["DragonFP.Status"],
01 FPCSLoadBA >EnumType["DragonFP.CSLoad"],
01 FPCSUAluBA >EnumType["DragonFP.CSUnload"],
01 FPCSUMultBA >EnumType["DragonFP.CSUnload"],
---
07
04 EPCmdA >EnumType["Dragon.PBusCommands"],
01 EPRejectB =BOOL, -- driven by IFP
03 EPFaultB =EnumType["Dragon.PBusFaults"], -- driven by IFP
<<>>
32 IPData =INT[32], -- address PhA, data PhB
04 IPCmdA >EnumType["Dragon.PBusCommands"],
01 IPRejectB <BOOL,
03 IPFaultB <EnumType["Dragon.PBusFaults"],
01 IPParityB <BOOL,
01 IPNPErrorB =BOOL,
<<>>
01 ResetAB <BOOL,
01 DHoldAB <BOOL,
01 DShiftAB <BOOL,
01 DExecuteAB <BOOL,
01 DNSelectAB <BOOL,
01 DDataInAB <BOOL,
01 DDataOutAB =BOOL,
01 RescheduleAB <BOOL,
01 PhA <BOOL,
01 PhB <BOOL,
---
121
MDF becomes just Field - eu bypassing used as temp register for Mul and Div
MQ no longer addressable:
MQ is not considered part of processor state
It is not addressed with LEUR/SEUR or LIFUR/SIFUR instructions
It is only used as a temp register for mult and div which are autonomous instructions
It is loaded by the microcode using the alu op PassLtWtMQ (bypassing not affected)
It is read by the microcode using the alu op RdMQ
Multiply
Step 0 - Load 0 into R1, Multiplier into MQ, initialize MultiplicandSign flag and branch out if zero
Unsigned
Lt _ S=Multiplicand
Rt _ S-1=Multiplier
aluop _ MulLdU
MicroBranch if aluout=0 (the product sign logic won't work if the M'cand=0)
R1 _ 0
MQ _ Multiplier
MCandS _ FALSE
ProdS _ FALSE
lastWasSub _ FALSE
S-1 = Product.msw _ R1
Signed
Lt _ S=Multiplicand
Rt _ S-1=Multiplier
aluop _ MulLdS
aluout _ Lt
MicroBranch if aluout=0 (the product sign logic won't work if the M'cand=0)
R1 _ 0
MQ _ Multiplier
MCandS _ LtSign
ProdS _ FALSE
lastWasSub _ FALSE
S-1 = Product.msw _ R1
Step 1..16
zero _ 000 or 111
two _ 100 or 011
sub _ 1xx
Lt _ S-1=Product.msw (right shift if two) (use old ProdS to do sign extend)
Rt _ S=Multiplicand or 0 (0 if zero)
aluop _ MulStep
aluout _ Lt (+/-) Rt - if sub
ProdS _ zero AND ProdS OR ~zero AND (sub xor MCandS)
R1|MQ _ aluout|Rt rt shift 1 if two and 2 if not (use new ProdS to do sign extend)
S-1=Product.msw _ R1
Step 17
Unsigned
zero _ xx0
Lt _ S-1=Product.msw
Rt _ S=Multiplicand or 0 (0 if zero)
aluop _ MulAdj
aluout _ Lt + Rt
MQ _ MQ
R1 _ aluout
S-1=Product.msw _ R1
Signed
instruction done
aluop _ RdMQ
S=Product.lsw _ MQ
Step 18 Unsigned
instruction done
aluop _ RdMQ
S=Product.lsw _ MQ
MicroBranch 1
instruction done
Lt _ S=Multiplicand = 0
Rt _ 0
aluop _ OR
aluout _ Lt
S-1 = Product.msw _ R1
Divide
Step 0
Lt _ S-2=Dividend MSW
Rt _ S-1=Dividend LSW
aluop _ DivLdDbl
aluout _ Lt
R1 _ aluout
MQ _ Rt
Zero _ FALSE
S+1=temporary Remainder location _ R1
Step 1
Unsigned
Lt _ S+1 = temporary Remainder location
Rt _ S = Divisor
aluop _ DivLdU
Cry aluout _ Lt-Rt (result must be negative)
TRAP if Cry
DivisorSign _ FALSE
DividendSign _ FALSE
Zero _ (aluout=0 OR Zero) AND MQSign
R1 | MQ _ LShift[ aluout | MQ | DivisorSign#Cry] (next op quaranteed to be add)
S+1=temporary Remainder location _ R1
Signed
Lt _ S+1 = temporary Remainder location
Rt _ S = Divisor
aluop _ DivLdS
aluout _ Lt
Cry _ ~ LtSign
DivisorSign _ RtSign
DividendSign _ LtSign
Zero _ (aluout=0 OR Zero) AND MQSign
R1 | MQ _ LShift[ aluout | MQ | DivisorSign#Cry]
S+1=temporary Remainder location _ R1
Step 2
Unsigned
Lt _ S+1 = temporary Remainder location
Rt _ S = Divisor
aluop _ DivStep
Cry aluout _ Lt (+/- - if MQSign) Rt
Zero _ (aluout=0 OR Zero) AND MQSign
R1 | MQ _ LShift[ aluout | MQ | DivisorSign#Cry]
S-1=Remainder _ R1
Signed
Lt _ S+1 = temporary Remainder location
Rt _ S = Divisor
aluop _ DivStep
Cry aluout _ Lt (+/- - if MQSign) Rt
TRAP IF
aluout=0 AND (DividendSign = DivisorSign)
aluout#0 AND (DividendSign # Cry)
Zero _ (aluout=0 OR Zero) AND MQSign
R1 | MQ _ LShift[ aluout | MQ | DivisorSign#Cry]
S-1=Remainder _ R1
Step 3..n
Lt _ S-1=Remainder
Rt _ S = Divisor
aluop _ DivStep
Cry aluout _ Lt (+/- - if MQSign) Rt
Zero _ (aluout=0 OR Zero) AND MQSign
R1 | MQ _ LShift[ aluout | MQ | DivisorSign#Cry]
S-1=Remainder _ R1
Step n+1
MDiv
Lt _ S-1=Remainder
Rt _ S = Divisor
aluop _ DivAdjM
Cry aluout _ Lt (+/- - if MQSign) Rt
Zero _ (aluout=0 OR Zero) (Update Zero before use below)
RemCorFF _
~DivisorSign ~Cry OR
DivisorSign Cry ~Zero OR
~Cry Zero OR
QCorFF _
DivisorSign Zero
R1 _ aluout
MQ _ LShift[ MQ | DivisorSign#Cry]
S-1=Remainder _ R1
RDiv
Lt _ S-1=Remainder
Rt _ S = Divisor
aluop _ DivAdjR
Cry aluout _ Lt (+/- - if MQSign) Rt
Zero _ (aluout=0 OR Zero) (Update Zero before use below)
RemCorFF _
~DividendSign ~Cry OR
DividendSign Cry ~Zero OR
~Cry Zero OR
QCorFF _
DivisorSign Zero OR
~DividendSign DivisorSign OR
DividendSign ~DivisorSign ~Zero
R1 _ aluout
MQ _ LShift[ MQ | DivisorSign#Cry]
S-1=Remainder _ R1
Step n+2
Lt _ S-1=Remainder
Rt _ 0 OR S=Divisor (IF RemCorFF)
aluop _ DivAdj
*** aluout _ Lt (+/- - if MQSign) Rt
Cry _ QCorFF
R1 _ aluout
MQ _ MQ
S-1=Remainder _ R1
Step n+3
R1 _ MQ
S-2=Quotient _ R1
Step n+4
Lt _ S-2=Quotient
Rt _ 0
Cry aluout _ Lt + Rt + Cry
R1 _ aluout
S-2=Quotient _ R1
FP and Fixed Mult/DivChanges
Notes to Russ
New DragOpsCross.ProcessorRegister
euStack (000), -- base of EU stack (128 regs)
euJunk (128), -- the non-matching EU register
eu129 (129), -- easily addressable spare (NA)
euMAR (130), -- MemoryAddressRegister
euField (131), -- Field register
euAux (132), -- base of EU auxilliary registers (16 regs)
eu148 (148), -- easily addressable spare (NA)
eu149 (149), -- easily addressable spare (NA)
eu150 (150), -- easily addressable spare (NA)
eu151 (151), -- easily addressable spare (NA)
euConstant (152), -- base of EU constant registers (12 regs)
euBogus (169), -- [euBogus..euLast] are not legal (NA)
euLast (239), -- last possible EU reg (NA)
ifuXBus (240), -- internal IFU register (X bus)
ifuLevel3LS (241), -- internal IFU register (level 3 L & S)
ifuYoungestL (242), -- youngest L in IFU stack
ifuYoungestPC (243), -- youngest PC in IFU stack
ifuEldestL (244), -- eldest L in IFU stack
ifuEldestPC (245), -- eldest PC in IFU stack (read removes, write adds)
ifuStatus (246), -- IFU status
ifuSLimit (247), -- stack limit register
ifuFPMaskFlags (248), -- floating point mask and flags
ifuFPMode (249), -- floating point mode register
ifuBogus (250), -- [ifuBogus..ifuLast] are not legal (NA)
ifu251 (251), -- easily addressable spare (NA)
ifuL (252), -- current L register (NA)
ifuS (253), -- current S register (NA)
ifuPC (254), -- current program counter (NA)
ifuLast (255) -- last possible IFU reg (NA)
New OB OpCode: FP
Redefined OpCode: DIV Quotient|Remainder = [S-2]|[S-1] _ [S-2][S-1]/[S-0] S_S-1
Change stack limit from 17 to 16
FP and Fixed Mult/DivChanges
Lizard
Mult, Div and FPOp's
Change stack limit from 17 to 16 when Russ does
DragOpsCross
DragOpsCross.ProcessorRegister {fpMaskFlags fpMode}
Dragon
add FPFault to Dragon.PBusFaults
add StoreFP, FetchFPAlu and FetchFPMult to PBusCommands
New EU ops: PassRt, PassLt, PassLtWtMQ, RdMQ, DivLast (MulStep and DivStep already there)
DragonImpl
DragonIFU
add spaces after :'s in DragonIFU
change euCacheCmd to euPBusCmd
DragonIFUImpl
add StoreFP, FetchFP* PBusCommands to IsRdCmd and IsWtCmd
DragonFP.mesa
DragonFPImpl.mesa
DragonMicrocode
change euCacheCmd to euPBusCmd
add XASources (7+9=16 => add one bit):
fpLdMode,
fpLdAMsw, fpLdALsw,
fpLdBMsw, fpLdBLsw,
fpUlMsw, fpUlLsw
DragonMicrocodeImpl
add FPOP
add MULT
add DIV
DragOpsCross.JBBformatRange => {
rj: DragOpsCross.RJBformat these can be removed
TRUSTED {rj _ LOOPHOLE[instruction]}; these can be removed
IFU Page Fault Must wait for possible CJump or MemRefFault to execute
Can XOP be one cycle
IFU
change EUWriteToCacheAB to EUWriteToPBusAB
add
FPStatusB >EnumType["DragonFP.Status"],
FPCSLoadAB <EnumType["DragonFP.CSLoad"],
FPCSUAluAB <EnumType["DragonFP.CSUnload"],
FPCSUMultAB <EnumType["DragonFP.CSUnload"]
IFetcher
IDecoder
Change stack limit from 17 to 16 when Russ does
IRegAddr
IPipe
Use PassRt EU Op
add
FPStatusB >EnumType["DragonFP.Status"],
FPCSLoadAB <EnumType["DragonFP.CSLoad"], function of PBusCmnds
FPCSUAluAB <EnumType["DragonFP.CSUnload"], function of PBusCmnds
FPCSUMultAB <EnumType["DragonFP.CSUnload"] function of PBusCmnds
add KBus drivers for fpControl
New EU ops: PassRt, PassLtWtMQ, RdMQ, DivLast
IStack
IFP
FP
add logging stuff
EU
EUWriteToPBusAB
New EU ops: PassRt, PassLtWtMQ, RdMQ, Mult, Div DivLast
KBus during Phase A
It is the responisbility of the Microcode (using multicycles) to insure that there is no conflict for the KBus when it is used at
level 4 to move data from the EU to the IFU. SIFUR instructions are assessed a 3 cycle penalty by this requirement. Since the
other instructions using the KBus at level4 (SJ, SFC and SFCI) are branching instructions, there is no penalty. When the KBus is
used in this way, the CAddr passed to the EU in the previous phase B is in the range of IFU Registers.
KBus conflicts caused by FP ops should never happen since the load signals are driven from level3 and the unload signals from level
2 (just like EUAluRtIsK).
Floating Point operation
The two floating point chips operate using a single phase clock which makes it's active transition between PhA and PhB. In order
to save about 12 to 15 pins (3 pins redundant), the KBus is used during PhA to move the load[0..5], unload[0..2] and function[0..5]
signals from the IFU to the FP chips. The 3 ChipSelect signals are driven over separate pins.
Reject and Fault occuring in the instruction preceding a FP op are handled correctly (it says here). That is, the Load Chip Select
signal is disabled during the next A,B cycle and the IFP section of the IFU knows to ignore a set mode function.
The only guaranteed state associated with FP operations is the Mode, Mask and Flag registers. There are no FP ops which allow
'partial' operations which assume the previous state of internal FP chip registers (ie AM, AL, BM, BL etc). Each FP op loads all
its operands from the stack, waits a function specific numer of cycles then moves any results back to the stack.
IFP
The IFP is a section of the IFU which deals with two sets of data:
It maintains a copy of the mode register.
Write: The mode register is written as a side affect of setting the mode registers in the two FP chips. When both the high order
Function bits (FPAlu, FPMult) are set and FPCSLoad is enabled then Function is interpreted as a new nibble in the Mode register as
described in the Weitek documentation.
Read: The mode register may be read using a LIFUR instruction (Lev0BAddr matches FPMode).
It maintains copies of the 16 bit Mask and Flag registers and issues Reject and FPFfault.
Write: CSUnLoad during PhA causes the floating point Status signals during PhB (1.5 cycles later) to be decoded. The three
unsticky flags (used for legal floating point comparisons) are cleared and the flag corresponding to the decoded status signal is
set. If any of the curent flags are not masked then Reject and FPFault are asserted. The reject causes the EU to freeze and not
store the FP data currently on the PBus, and the fault causes the IDecoder logic during the next phase A to generate a FP trap
exception.
Write: The Mask and Flag registers may also be written using a SIFUR instruction (Lev3Caddr matches FPMaskFlag).
Read: The Mask and Flag registers may be read using a LIFUR instruction (Lev0BAddr matches FPMaskFlag).
FP format: FP alpha
alpha: BYTE = FPMult: BOOL, FPAlu: BOOL, FPFunction: CARDINAL[0..64)
IF FPMult AND FPAlu
THEN Set Mode
ELSE Execute FPFunction for specified device. (one BOOL must be TRUE)
Binary op operands (A op B) are stacked in the EU with A pushed first.
Double precision operands are stacked in the EU with the most significant word pushed first.
alpha for ALU OPs
Subtract Compare (returns only status)
01 00 000 0 F32 - F32 01 10 000 0 F32 - F32
01 00 000 1 F64 - F64 01 10 000 1 F64 - F64
01 00 001 0 |F32 - F32| 01 10 001 0 -F32 + F32
01 00 001 1 |F64 - F64| 01 10 001 1 -F64 + F64
01 00 010 0 01 10 010 0 |F32| - |F32|
01 00 010 1 01 10 010 1 |F64| - |F64|
01 00 011 0 01 10 011 0
01 00 011 1 01 10 011 1
01 00 100 0 -F32 + 0 01 10 100 0 F32 - 0
01 00 100 1 -F64 + 0 01 10 100 1 F64 - 0
01 00 101 0 01 10 101 0
01 00 101 1 01 10 101 1
01 00 110 0 -F32 + 0 01 10 110 0
01 00 110 1 -F64 + 0 01 10 110 1
01 00 111 0 01 10 111 0
01 00 111 1 01 10 111 1
Add Convert
01 01 000 0 F32 + F32 01 11 000 0 U32 to D32 (exact)
01 01 000 1 F64 + F64 01 11 000 1 U64 to D64 (exact)
01 01 001 0 |F32 + F32| 01 11 001 0 D32 to W32
01 01 001 1 |F64 + F64| 01 11 001 1 D64 to W64
01 01 010 0 |F32| + |F32| 01 11 010 0 U32 to D32 (inexact)
01 01 010 1 |F64| + |F64| 01 11 010 1 U64 to D64 (inexact)
01 01 011 0 01 11 011 0
01 01 011 1 01 11 011 1
01 01 100 0 F32 + 0 01 11 100 0 F32 - I32
01 01 100 1 F64 + 0 01 11 100 1 F64 - I32
01 01 101 0 01 11 101 0 I32 - F32
01 01 101 1 01 11 101 1 I32 - F64
01 01 110 0 |F32| + 0 01 11 110 0 F32 - F64
01 01 110 1 |F64| + 0 01 11 110 1 F64 - F32
01 01 111 0 01 11 111 0
01 01 111 1 01 11 111 1
alpha for Mult OPs
10 xxx 000 F32 * F32
10 xxx 001 F64 * F64
10 xxx 010 W32 * F32
10 xxx 011 W64 * F64
01 xxx 100 F32 * W32
01 xxx 101 F64 * W64
01 xxx 110 W32 * W32
01 xxx 111 W64 * W64
10 000 xxx A * B
10 001 xxx |A| * B
10 010 xxx A * |B|
10 011 xxx |A| * |B|
01 100 xxx - A * B
01 101 xxx -|A| * B
01 110 xxx - A * |B|
01 111 xxx -|A| * |B|
alpha for Set Mode
1100RRIF = mode0
RR Floating point rounding mode
00 Round toward nearest
01 Round toward zero
10 Round toward Positive infinity
11 Round toward negative infinity
I Fixed point rounding mode
0 Round according to Floating point rounding mode
1 Round toward zero
F Fast mode (this is not in the doc but is supposed to exist)
0 IEEE mode
1 Flush denormalized operands and results to zero
1101AAxx = mode1
AA Multiplier Accumulation rate (does this really exist?)
00 Clock/1
01 Clock/2
10 Clock/3
11 Clock/4
Types of FPFunctions => separate decoding in the Decoder PLA
Operands Result Time Cycles
Set Mode - - 120ns 2
Convert Unary Single one Single Double 240ns 3
Convert Unary Double one Double Single 240ns 3
Compare Unary Single one Single - 240ns 3
Compare Unary Double one Double - 240ns 3
Compare Binary Single two Single - 240ns 3
Compare Binary Double two Double - 240ns 3
Alu Unary Single one Single Single 240ns 3
Alu Unary Double one Double Double 240ns 3
Alu Binary Single two Single Single 240ns 3
Alu Binary Double two Double Double 240ns 3
Mult Binary Single two Single Single 240ns 3
Mult Binary Double two Double Double 360 ns 4
Cycle 0 1 2 3 4 5 6 7 8 9
sglUnCom AM<S0 Stat S_S-1
sglUnAlu AM<S0 S0<AM S_S-0
sglUnCvt AM<S0 S0<AM S+<AL S_S+1
dblUnCom AL<S0 AM<S1 Stat S_S-2
dblUnAlu AL<S0 AM<S1 S1<AM S0<AL S_S-0
dblUnCvt AL<S0 AM<S1 S1<AM S_S-1
sglBiCom BM<S0 AM<S1 Stat S_S-2
sglBiAlu BM<S0 AM<S1 S1<AM S_S-1
sglBiMul BM<S0 AM<S1 S1<MM S_S-1
dblBiCom BL<S0 BM<S1 AL<S2 AM<S3 Stat S_S-4
dblBiAlu BL<S0 BM<S1 AL<S2 AM<S3 S3<AM S2<AL S_S-2
dblBiMul BL<S0 BM<S1 AL<S2 AM<S3 S3<MM S2<ML S_S-2
01 00 0. .0 sglBiAlu
01 00 0. .1 dblBiAlu
01 00 1. .0 sglUnAlu
01 00 1. .1 dblUnAlu
01 01 0. .0 sglBiAlu
01 01 0. .1 dblBiAlu
01 01 1. .0 sglUnAlu
01 01 1. .1 dblUnAlu
01 10 0. .0 sglBiCom
01 10 0. .1 dblBiCom
01 10 1. .0 sglUnCom
01 10 1. .1 dblUnCom
01 11 0. .0 sglUnAlu
01 11 0. .1 dblUnAlu
01 11 10 00 sglUnAlu
01 11 10 01 dblUnCvt
01 11 10 10 sglUnAlu
01 11 10 11 sglUnCvt
01 11 11 00 sglUnCvt
01 11 11 01 dblUnCvt
01 11 11 10 *
01 11 11 11 *
10 .. .. .0 sglBiMult
10 .. .. .1 dblBiMult
11 .. .. .. dblBiMult
**************
01 00 0. .0 sglBiAlu
01 01 0. .0 sglBiAlu
01 00 1. .0 sglUnAlu
01 01 1. .0 sglUnAlu
01 11 0. .0 sglUnAlu
01 11 10 00 sglUnAlu
01 11 10 10 sglUnAlu
01 00 1. .1 dblUnAlu
01 01 1. .1 dblUnAlu
01 11 0. .1 dblUnAlu
01 00 0. .1 dblBiAlu
01 01 0. .1 dblBiAlu
01 10 0. .0 sglBiCom
01 10 0. .1 dblBiCom
01 10 1. .0 sglUnCom
01 10 1. .1 dblUnCom
01 11 10 11 sglUnCvt
01 11 11 00 sglUnCvt
01 11 10 01 dblUnCvt
01 11 11 01 dblUnCvt
01 11 11 10 *
01 11 11 11 *
10 .. .. .0 sglBiMult
10 .. .. .1 dblBiMult
11 .. .. .. dblBiMult
**************
01 0. 0. .0 sglBiAlu
01 0. 1. .0 sglUnAlu
01 11 0. .0 sglUnAlu
01 11 10 .0 sglUnAlu
01 0. 1. .1 dblUnAlu
01 11 0. .1 dblUnAlu
01 0. 0. .1 dblBiAlu
01 10 0. .0 sglBiCom
01 10 0. .1 dblBiCom
01 10 1. .0 sglUnCom
01 10 1. .1 dblUnCom
01 11 1. 11 sglUnCvt
01 11 11 .0 sglUnCvt
01 11 1. 01 dblUnCvt
10 .. .. .0 sglBiMult
10 .. .. .1 dblBiMult
11 .. .. .. dblBiMult
First 16 ALUOps 16 RR instructions 300B - 317B
Or (0) op47 dROR dRRX (gets mapped to VAdd)
And (1) BndChk dRAND dRBC
Xor (2) UAdd dRXOR dRUADD
(3) USub dRUSUB
FOP (4) VAdd dRFU dRVADD
FOPK (5) VSub dRVSUB
SAdd (6) LAdd dRADD dRLADD
SSub (7) LSub dRSUB dRLSUB
dRBC also get BC condition select
False (0) x
EZ (1) dRJEB
LZ (2) dRJLB
LE (3) dRJEB
True (4) dRJEB
NE (5) dRJEB
GE (6) dRJEB
GZ (7) dRJEB
OvFl (8)
BC (9)
IL (10)
DivOvFl (11)
NotOvFl (12)
NotBC (13)
NotIL (14)
op57 (15)
<<IFUSchNotes.tioga>>
<<Don Curry April 21, 1987 3:01:03 pm PST>>
Static Check messages
Heart - these need to be checked - has only one connection
StackPass[0..31]
DataColumn
DShWt
InstrReg
PCForm
Stack
Op47GndAlphaBetaBA [0..32)
LSForm
ABForm
ControlPipe
DShWt
FourthByte [1..7]
Lichen
FetchIndexingRot90 passed
StackIndexingRot90 passed
InstrReg - FetchInst (16 latches (blank) look identical)
OK
And Tiles - Extracting [CMosB] cell (bbox: [0, 0, 128, 64], instances: 7, 9, ?, ?) Met2 and poly
Fusion by name for 'in1' in cell ''.
Fusion by name for 'in0' in cell ''.
StackIndexing
Deleting row 4 SB node: DiffBCryOut[0]
Deleting row 16 SB node: StackIncrCryOut[0]
FetchIndexing
Deleting row 3 SB node: FetchBytesM1CryOut[0]
Deleting row 10 SB node: FetchRdSumCryOut[0]
Deleting row 16 SB node: FetchWtSumCryOut[0]
InstrReg.icon
Deleting row 7 SB node: FetchAddrBA[31]
Deleting row 7 SB node: FetchAddrBA[30]
FetchBuf - Extracting [CMosB] cell (bbox: [0, 0, 3440, 1088], instances: 1086)
Fusion by name for 'wtWd' in cell ''.
XaForm.mask
Fusion by name for 'AlphaAB[7]' in cell 'XaForm.mask'.
Fusion by name for 'BetaAB[7]' in cell 'XaForm.mask'.
PCForm.icon (PCFormTop)
Deleting row 4 SB node: OpAlphaBetaBA[0..3]
Deleting row 4 SB node: OpAlphaBetaBA[8..15]
Deleting row 11 SB node: AlphaBetaGamaDeltaAB[16..31]
Stack
PreStatStkTopAB[0..7, 16..23]
LSForm.icon
?
ABForm.icon
Deleting row 9 SB node: StackGapBA[0, 4..7]
Deleting row 9 SB node: IOOout[3..7]
Deleting row 15 SB node: StateBA[0]
ControlPipe.icon
Deleting row 0 SB node: [0..6]
Deleting row 11 SB node: [0,5]
Deleting row 14 SB node: [0..3, 6..7]
Deleting row 14 SB node: EUAluOp0BA[0..3]
Deleting row 14 SB node: EUCondSel0BA[0..3]
Deleting row 14 SB node: OrOut[0,1,6,7]
Mint - OK
ControlPipeMain).EUAluOp0B[0..3]:Vdd
ControlPipeMain).EUCondSel0B[0..3]:Vdd
PCFormTop).TrapPC[**]
NotOK
combine sboxes where possible
Remove excess outputs
InstrDecode)/3(InstrDecode4)*1.out.SSourceRt[0]:Gnd
InstrDecode)/4(InstrDecode3)*1.out.CRegRt[0]:Gnd
InstrDecode)/4(InstrDecode3)*1.out.CRegRt[2]:Gnd
InstrDecode)/4(InstrDecode3)*1.out.CRegRt[4]:Gnd
InstrDecode)/5(InstrDecode2)*1.out.BRegRt[0]:Gnd
InstrDecode)/5(InstrDecode2)*1.out.BRegRt[2]:Gnd
InstrDecode)/5(InstrDecode1)*1.out.ARegLt[2]:Gnd
InstrDecode)/5(InstrDecode1)*1.out.ARegRt[1,2,4,5]:Gnd
???
Heart.bind)*1.OpABJmpSpec[0..2]:NotLdFmFet
InstrDecode)/2(InstrDecode5)/1(IFUPLAInstrDecode5Body)*2.[34..39]:Gnd
InstrDecode)/4(InstrDecode3)/1(IFUPLAInstrDecode3Body)*2.[59..61]:Gnd
InstrDecode)/5(InstrDecode2)/1(IFUPLAInstrDecode2Body)*2.[48..53,55]:Gnd
InstrDecode)/5(InstrDecode1)/1(IFUPLAInstrDecode1Body)*2.[29..34]:Gnd
IFUStats.tioga
Without TilingClass cell
IFU.core!15 5619760 08-Jun-87 22:58:25 PDT
DataColumn.core!11 2676651 07-Jun-87 19:00:45 PDT
LeftColumn.core!14 1601305 06-Jun-87 23:27:23 PDT
RightColumn.core!17 2727822 08-Jun-87 19:14:12 PDT
IFULayout.dale!10 2566698 08-Jun-87 23:18:03 PDT
DataColumnLayout.dale!11 924487 07-Jun-87 19:09:25 PDT
LeftColumnLayout.dale!14 463509 06-Jun-87 23:31:57 PDT
RightColumnLayout.dale!15 890363 08-Jun-87 19:21:48 PDT
IFUShell.dale!10 19584 08-Jun-87 23:17:35 PDT
DataColumnShell.dale!11 138441 07-Jun-87 19:08:50 PDT
LeftColumnShell.dale!14 19290 06-Jun-87 23:31:52 PDT
RightColumnShell.dale!15 23767 08-Jun-87 19:21:41 PDT
IFU.core!16 5620190 08-Jul-87 13:44:42 PDT
DataColumn.core!12 2683285 08-Jul-87 09:46:51 PDT
LeftColumn.core!15 1603075 08-Jul-87 01:05:13 PDT
RightColumn.core!18 2728630 08-Jul-87 00:09:24 PDT
IFULayout.dale!11 2566645 08-Jul-87 13:58:35 PDT
DataColumnLayout.dale!12 924434 08-Jul-87 09:54:52 PDT
LeftColumnLayout.dale!15 463524 08-Jul-87 01:09:44 PDT
RightColumnLayout.dale!16 890313 08-Jul-87 00:16:52 PDT
IFUShell.dale!11 19583 08-Jul-87 13:58:15 PDT
DataColumnShell.dale!12 138465 08-Jul-87 09:54:24 PDT
LeftColumnShell.dale!15 19289 08-Jul-87 01:09:39 PDT
RightColumnShell.dale!16 23767 08-Jul-87 00:16:45 PDT
IFU 80 min + ??? (restarted)
DataColumn 50 min
LeftColumn 60 min
RightColumn 140 min
With TilingClass cell
LeftColumnLayout.dale!16 141781 bytes = 1/ 7.1 previous size <<<
RightColumnLayout.dale!17 124972 bytes = 1/ 3.3 previous size
LeftColumn.core!16 1029394 bytes = 1/ 1.6 previous size
RightColumn.core!19 1340579 bytes = 1/ 2.0 previous size
LeftColumn 30 min = 1/ 2.0 previous time
RightColumn 40 min = 1/ 3.5 previous time
With TilingClass cell and one VM
IFULayout.dale 1415005 bytes = 1/ 1.8 previous size
IFU.core 5560238 bytes = 1/ 1.0 previous size
IFU 180 min = 1/ 2 0+ previous time
plus CDRoutingObjects in DP => faster layout extraction
IFULayout.dale 1415427 bytes
IFU.core 5410101 bytes
IFU 192 min
Extraction: 48
Layout: 124
Save: 20