[Indigo]<Dragon7.0>IFUPublic>IFUPublicImpl.mesa!1

IFUPublicImpl.mesa

Don Curry April 2, 1987 9:36:57 am PST

DIRECTORY Core, CoreCreate, CoreOps, IFUPublic, Ports, REFBit, Rosemary;

IFUPublicImpl: CEDAR PROGRAM

IMPORTS CoreCreate, CoreOps, Ports, REFBit, Rosemary

EXPORTS IFUPublic =

BEGIN

PortWire: PUBLIC PROC

[init: BOOL, name: Core.ROPE, size: NAT𡤀, dr: Ports.Drive←none, pwrVal: Ports.Level ← L]

RETURNS[wire: Core.Wire] = {

wire ← CoreCreate.Seq[name, (IF size=1 THEN 0 ELSE size)];

IF NOT init THEN RETURN[wire];

[] ← Ports.InitPort[

wire: wire,

levelType: (SELECT size FROM 0,1=>b, <=16=>c, <=32=>lc, ENDCASE=>ERROR),

initDrive: dr ];

[] ← Ports.InitTesterDrive[

wire: wire,

initDrive: (SELECT dr FROM none=>force, force, expect => none, ENDCASE=>expect)];

IF dr=infinite THEN [] ← Rosemary.SetFixedWire[wire, pwrVal]};

IfuInitializedPublic: PUBLIC PROC[init: BOOL ← TRUE] RETURNS[public: Core.Wire] = {

II: TYPE = IFUPublic.II;

ii: II ← LAST[II];

public ← CoreOps.CreateWires[ii.ORD+1];

public[II[KBus ].ORD] ← PortWire[init, "KBus", 32, drive ];

public[II[EUAluOp ].ORD] ← PortWire[init, "EUAluOp", 4, drive ];

public[II[EUCondSel ].ORD] ← PortWire[init, "EUCondSel", 4, drive ];

public[II[EUCondition ].ORD] ← PortWire[init, "EUCondition"];

public[II[EURdFromPBus ].ORD] ← PortWire[init, "EURdFromPBus", 1, drive ];

public[II[EUWriteToPBus ].ORD] ← PortWire[init, "EUWriteToPBus", 1, drive ];

public[II[UserMode ].ORD] ← PortWire[init, "UserMode", 1, drive ];

public[II[DPCmd ].ORD] ← PortWire[init, "DPCmd", 8, drive ];

public[II[DPReject ].ORD] ← PortWire[init, "DPReject"];

public[II[DPFault ].ORD] ← PortWire[init, "DPFault", 4];

public[II[IPCmdFetch ].ORD] ← PortWire[init, "IPCmdFetch", 1, drive ];

public[II[IPReject ].ORD] ← PortWire[init, "IPReject"];

public[II[IPFaulting ].ORD] ← PortWire[init, "IPFaulting"];

public[II[IPData ].ORD] ← PortWire[init, "IPData", 32];

public[II[DShA ].ORD] ← PortWire[init, "DShA"];

public[II[DShB ].ORD] ← PortWire[init, "DShB"];

public[II[DShRd ].ORD] ← PortWire[init, "DShRd"];

public[II[DShWt ].ORD] ← PortWire[init, "DShWt"];

public[II[DShIn ].ORD] ← PortWire[init, "DShIn"];

public[II[DShOut ].ORD] ← PortWire[init, "DShOut", 1, drive ];

public[II[Reset ].ORD] ← PortWire[init, "Reset"];

public[II[Reschedule ].ORD] ← PortWire[init, "Reschedule"];

public[II[Clk ].ORD] ← PortWire[init, "Clk"];

public[II[PhAOut ].ORD] ← PortWire[init, "PhAOut", 1, drive ];

public[II[PhBOut ].ORD] ← PortWire[init, "PhBOut", 1, drive ];

public[II[PhA ].ORD] ← PortWire[init, "PhA"];

public[II[PhB ].ORD] ← PortWire[init, "PhB"];

public[II[VbbGen ].ORD] ← PortWire[init, "VbbGen", 1, drive ];

public[II[Vbb ].ORD] ← PortWire[init, "Vbb", 1, infinite, H];

public[II[Vdd ].ORD] ← PortWire[init, "Vdd", 1, infinite, H];

public[II[Gnd ].ORD] ← PortWire[init, "Gnd", 1, infinite, L];

public[II[PadVdd ].ORD] ← PortWire[init, "PadVdd", 1, infinite, H];

public[II[PadGnd ].ORD] ← PortWire[init, "PadGnd", 1, infinite, L]};

scanDrInv: PUBLIC IFUPublic.ScanRef ← ScanDrInv[];

ScanDrInv: PUBLIC PROC[scan: IFUPublic.ScanRef ← NIL] RETURNS[IFUPublic.ScanRef] = {

logicalBit: CARDINAL ← 0;

format: REFBit.Format;

IF scan=NIL THEN scan ← NEW[IFUPublic.ScanRec];

format ← REFBit.Desc[scan].fieldForm;

FOR fldFrmIdx: CARDINAL IN [0..format.size) DO -- detects Decoded Enumerated Type LSBs

field: REFBit.FormatRec ← format[fldFrmIdx];

logicalBit ← logicalBit + field.bitSize;

IF field.bitSize>1 AND

field.name=NIL AND

field.nameInv#NIL

THEN REFBit.Set[scan, logicalBit-1, NOT REFBit.Get[scan, logicalBit-1]] ENDLOOP;

scan.MPOut.notBcLoadStage1 ← NOT scan.MPOut.notBcLoadStage1;

scan.FCOut.notInstReady ← NOT scan.FCOut.notInstReady;

RETURN[scan]};

SetScanBit: PUBLIC PROC[scan: IFUPublic.ScanRef, bit: NAT, val: BOOL] = {

inv: BOOL ← REFBit.Get[scanDrInv, bit];

REFBit.Set[scan, bit, val#inv]};

GetScanBit: PUBLIC PROC[scan: IFUPublic.ScanRef, bit: NAT] RETURNS[ val: BOOL] = {

inv: BOOL ← REFBit.Get[scanDrInv, bit];

val ← inv#REFBit.Get[scan, bit]};

END.