[Indigo]<Dragon7.0>IFUPLA>IFUPLAMainPipeControlImpl.mesa!2

IFUPLAMainPipeControlImpl.mesa

Last edited by McCreight, June 6, 1986 5:43:46 pm PDT

Last edited by Curry, September 14, 1986 4:15:52 pm PDT

Don Curry March 9, 1987 5:06:25 pm PST

DIRECTORY

Commander, IFUPLAMainPipeControl, IO, PLAOps, Rope;

IFUPLAMainPipeControlImpl: CEDAR PROGRAM

IMPORTS Commander, IO, PLAOps, Rope =

BEGIN OPEN PO: PLAOps;

MainPipeControlIn: TYPE = IFUPLAMainPipeControl.MainPipeControlIn;

MainPipeControlOut: TYPE = IFUPLAMainPipeControl.MainPipeControlOut;

CondEffect: TYPE = IFUPLAMainPipeControl.CondEffect;

MainPipeControlPLA: PO.PLA;

MainPipeControlProc: PROC[argRec: MainPipeControlIn] RETURNS [resRec: MainPipeControlOut] = {

arg: REF MainPipeControlIn ← NARROW[MainPipeControlPLA.data];

res: REF MainPipeControlOut ← NARROW[MainPipeControlPLA.out];

arg^ ← argRec; PO.GetOutForData[MainPipeControlPLA]; resRec ← res^};

condEffectIsSig: CondEffect ← LAST [CondEffect];

forceBubble: MainPipeControlOut =

[microExcptJmp: bubble, except: [specialCode, bubble]];

GenPhBOutputs: PROC = {

maskableTrap: PO.BoolExpr ←

PO.And[

BETrue[[trapsEnabled2: TRUE]],

PO.Or[

BETrue[[eStkOverflow2: TRUE]],

PO.And[

BETrue[[instStarting2: TRUE]],

BETrue[[rschWaitingIn: TRUE]] ],

PO.And[

BETrue[[push2: TRUE]],

BETrue[[iStkNearlyFull: TRUE]] ] ] ];

stage2Failed: PO.BoolExpr ← PO.Or[

BETrue[[reset: TRUE]],

BETrue[[stage2BAbort: TRUE]],

PO.And[

BETrue[[eUCondition2: TRUE]],

BE[m:[condEffect2: condEffectIsSig], d:[condEffect2: macroTrap]] ],

maskableTrap ];

stage2FailedOr1Hold: PO.BoolExpr ← PO.Or[

stage2Failed,

BETrue[[stage1BHold: TRUE]] ];

loadStage1: PO.BoolExpr ← PO.Or[

BEFalse[[microExcptJmpBubble: TRUE]], BETrue[[reset: TRUE]] ];

loadStages23: PO.BoolExpr ←

PO.Or[ BEFalse[[dPReject: TRUE]], BETrue[[reset: TRUE]] ];

Set[ s: stage2Failed, out: [stage3A: abort ] ];

Set[ s: stage2FailedOr1Hold, out: [stage2A: bubble ] ];

Set[ s: loadStage1, out: [loadStage1: TRUE ] ];

Set[ s: loadStages23, out: [loadStage2: TRUE ] ];

Set[ s: loadStages23, out: [loadStage3: TRUE ] ]};

Set[ s: BETrue[[x2ASrcLit1: TRUE]], out: [x2ASrcLit2: TRUE ] ]};

GenPhAOutputs: PROC = {

cur, temp: PO.BoolExpr;

rschClear is generated below and fed back in the same phase A (since it would be expensive to invert its generating condition). It is just used to compute the newRschWaiting.

rschWaitingIn: PO.BoolExpr ← BETrue[[rschWaitingIn: TRUE]];

newRschWaiting: PO.BoolExpr ← PO.And[

BEFalse[[reset: TRUE]],

BEFalse[[rschClearIn: TRUE]],

PO.Or[ rschWaitingIn, BETrue[[reschedule: TRUE]] ] ];

notCondEffect1Bubble : PO.BoolExpr ←

PO.Or[

BETrue[[reset: TRUE]],

PO.Not[BE[m: [condEffect1: condEffectIsSig], d: [condEffect1: bubble]]] ];

stage1BHolding: PO.BoolExpr ← PO.Or[

BETrue[[reset: TRUE]],

PO.And[

notCondEffect1Bubble,

PO.Or[ BETrue[[stage1BHold: TRUE]], BETrue[[dPReject: TRUE]] ] ] ];

stage1BHolding: PO.BoolExpr ← PO.And[

BEFalse[[reset: TRUE]],

notCondEffect1Bubble,

PO.Or[ BETrue[[stage1BHold: TRUE]], BETrue[[dPReject: TRUE]] ] ];

eUStkOverflow: PO.BoolExpr ← PO.And[

BETrue[[trapsEnabled2: TRUE]],

BETrue[[eStkOverflow2: TRUE]] ];

ifuStkOverflow: PO.BoolExpr ← PO.And[

BETrue[[trapsEnabled2: TRUE]],

BETrue[[iStkNearlyFull: TRUE]],

PO.Or[

BETrue[[dPFaulting: TRUE]],

PO.And[

BEFalse[[dPReject: TRUE]],

PO.Or[

BETrue[[push2: TRUE]],

BETrue[[eStkOverflow2: TRUE]],

BETrue[[instFault2: TRUE]],

PO.And[BETrue[[instStarting2: TRUE]], rschWaitingIn],

PO.And[

BETrue[[eUCondition2: TRUE]],

BE[ m: [condEffect2: condEffectIsSig], d: [condEffect2: macroTrap] ] ] ] ] ] ];

interlock: PO.BoolExpr ← PO.And[

PO.Or[

BETrue[[stage1BHold: TRUE]],

PO.And[

BETrue[[stage1HoldIfReject: TRUE]],

BETrue[[dPReject: TRUE]] ] ],

notCondEffect1Bubble ];

interlock: PO.BoolExpr ← PO.And[

PO.Or[

BETrue[[stage1BHold: TRUE]],

BETrue[[dPReject: TRUE]] ],

notCondEffect1Bubble ];

Set[ s: newRschWaiting, out:[ rschWaiting: TRUE ] ];

Set[ s: BETrue[[dPFaulting: TRUE]], out:[ stage3BCPipe: abort ] ];

Set[ s: stage1BHolding, out:[

stage1BHolding: TRUE,

notBcLoadStage1: TRUE ] ];

Reset

Set[s: BETrue[[reset: TRUE]], out:[

stage2B: abort,

microExcptJmp: resetting,

except: [specialCode, reset] ] ];

cur ← BEFalse[[reset: TRUE]];

Intermediate cycle of protected microinstruction sequence

Set[s: PO.And[cur, BETrue[[protMicroCycle: TRUE]]], out:[

microExcptJmp: none,

except: [specialCode, none] ] ];

cur ← PO.And[cur, BEFalse[[protMicroCycle: TRUE]]];

IFU stack overflow

Set[s: PO.And[cur, ifuStkOverflow], out:[

stage2B: abort,

microExcptJmp: trap,

except: [specialCode, iStkOFlow] ] ];

cur ← PO.And[cur, PO.Not[ifuStkOverflow]];

Data PBus Fault, pipe stage 3

Set[s: PO.And[cur, BETrue[[dPFaulting: TRUE]]], out:[

stage2B: abort,

microExcptJmp: trap,

except: [dpFault] ] ];

cur ← PO.And[cur, BEFalse[[dPFaulting: TRUE]]];

Reject

Set[s: PO.And[cur, BETrue[[dPReject: TRUE]], notCondEffect1Bubble], out: forceBubble ];

cur ← PO.And[cur, BEFalse[[dPReject: TRUE]]];

ALU Condition, pipe stage 2

temp ← PO.And[cur, BETrue[[eUCondition2: TRUE]]];

Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: macroTrap], out:[

stage2B: abort,

microExcptJmp: trap,

except: [condCode] ] ];

Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: macroJump], out:[

stage2B: abort,

microExcptJmp: cJump,

except: [specialCode, cJump] ] ];

Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: microJump], out:[

microExcptJmp: microJump ] ];

cur ← PO.And[cur, BEFalse[[eUCondition2: TRUE]]];

EU stack overflow, pipe stage 2

Set[s: PO.And[cur, eUStkOverflow], out:[

stage2B: abort,

microExcptJmp: trap,

except: [specialCode, eStkOFlow] ] ];

cur ← PO.And[cur, PO.Not[eUStkOverflow]];

Pipe Interlock

Set[s: PO.And[cur, interlock], out: forceBubble ];

cur ← PO.And[cur, PO.Not[interlock]];

cur ← PO.And[cur, BETrue[[instStarting2: TRUE]] ];

Reschedule Waiting, pipe stage 2

Set[s: PO.And[cur, BETrue[[trapsEnabled2: TRUE]], rschWaitingIn], out:[

rschClear: TRUE,

stage2B: abort,

microExcptJmp: trap,

except: [specialCode, rschlWait] ]];

cur ← PO.And[cur, PO.Or[PO.Not[rschWaitingIn], BEFalse[[trapsEnabled2: TRUE]]]];

Instruction Fetch Fault, pipe stage 2

Set[s:cur, m:[instFault2: TRUE], d:[instFault2: TRUE], out:[

stage2B: abort,

microExcptJmp: trap,

except: [specialCode, ipFault] ]];

cur ← PO.And[cur, BEFalse[[instFault2: TRUE]]];

ELSE new unexceptional microinstruction [ ]

};

BE: PROC [m, d: MainPipeControlIn ] RETURNS[ PO.BoolExpr ] = {

mRef: REF MainPipeControlIn ← NARROW[MainPipeControlPLA.mask];

dRef: REF MainPipeControlIn ← NARROW[MainPipeControlPLA.data];

mRef^ ← m; dRef^ ← d; RETURN[PO.GetBEForDataMask[MainPipeControlPLA]]};

BETrue: PROC [ d: MainPipeControlIn ] RETURNS[ PO.BoolExpr ] = { RETURN[ BE[d,d] ] };

BEFalse: PROC [ d: MainPipeControlIn ] RETURNS[ PO.BoolExpr ] = { RETURN[ BE[d,[]] ] };

Set: PROC [s: PO.BoolExpr ← NIL, m, d: MainPipeControlIn ← [ ], out: MainPipeControlOut] = {

res: REF MainPipeControlOut ← NARROW[MainPipeControlPLA.out];

s ← IF s=NIL THEN BE[m,d] ELSE PO.And[s, BE[m,d] ];

res^ ← out; PO.SetOutForBE[MainPipeControlPLA, s]};

GenMainPipeControl: Commander.CommandProc = {

MainPipeControlPLA ← PO.NewPLA[

name.Cat[".MainPipeControlIn"],

name.Cat[".MainPipeControlOut"],

name ];

GenPhBOutputs[];

GenPhAOutputs[];

[ ] ← PO.ConvertTermListToCompleteSum[MainPipeControlPLA.termList, FALSE, FALSE, cmd.out];

[ ] ← PO.FindAMinimalCover[MainPipeControlPLA.termList, 120, cmd.out];

PO.WritePLAFile[MainPipeControlPLA, NIL, cmd.out] };

ReadMainPipeControl: Commander.CommandProc =

{MainPipeControlPLA ← PO.ReadPLAFile[name, cmd.out]};

name: IO.ROPE = "IFUPLAMainPipeControl";

Commander.Register[key:"GenMainPipeControl", proc: GenMainPipeControl];

Commander.Register[key:"ReadMainPipeControl", proc: ReadMainPipeControl];

END.